MC9S12KG128_10 Datasheet, PDF (81/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x000D
R
0
0
0
0
0
0
0
0
RESERVED2
W
0x000E
R
0
0
0
0
0
0
0
0
RESERVED3
W
0x000F
R
0
0
0
0
0
0
0
0
RESERVED4
W
= Unimplemented or Reserved
Figure 2-3. FTS128K1ECC Register Summary (continued)
2.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Module Base + 0x0000
7
6
5
4
3
2
R FDIVLD
W
PRDIV8
FDIV5
FDIV4
FDIV3
FDIV2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-4. Flash Clock Divider Register (FCLKDIV)
1
FDIV1
0
0
FDIV0
0
All bits in the FCLKDIV register are readable, bits 6-0 are write once and bit 7 is not writable.
Table 2-5. FCLKDIV Field Descriptions
Field
Description
7
FDIVLD
6
PRDIV8
Clock Divider Loaded.
0 Register has not been written.
1 Register has been written to since the last reset.
Enable Prescalar by 8.
0 The oscillator clock is directly fed into the clock divider.
1 The oscillator clock is divided by 8 before feeding into the clock divider.
5-0
FDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz–200 kHz. The maximum divide ratio is 512. Please refer to Section 2.4.1.1, “Writing the
FCLKDIV Register” for more information.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
81