MC9S12KG128_10 Datasheet, PDF (71/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1)
1.6.2 Resets
Resets are a subset of the interrupts featured inTable 1-12. The different sources capable of generating a
system reset are summarized in Table 1-13.
Table 1-13. Reset Summary
Reset
Power-on Reset
External Reset
Low Voltage Reset
Clock Monitor Reset
COP Watchdog Reset
Priority
1
1
1
2
3
Source
CRG Module
RESET pin
VREG Module
CRG Module
CRG Module
Vector
0xFFFE, 0xFFFF
0xFFFE, 0xFFFF
0xFFFE, 0xFFFF
0xFFFC, 0xFFFD
0xFFFA, 0xFFFB
1.6.2.1 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module block description chapters for register reset states.
Refer to the PIM block description chapter for reset configurations of all peripheral module ports.
Refer to Table 1-5 for locations of the memories depending on the operating mode after reset.
The RAM array is not automatically initialized out of reset.
1.7 ATD External Trigger Input Connection
The ATD module includes external trigger input ETRIG. On MC9S12KG128, the ETRIG input is tied to
GND.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
71