MC9S12KG128_10 Datasheet, PDF (151/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.2.6
Chapter 4 Port Integration Module (PIM9KG128V1)
Port S Polarity Select Register (PPSS)
Module Base + 0x000D
7
R
PPSS7
W
6
PPSS6
5
PPSS5
4
PPSS4
3
PPSS3
2
PPSS2
1
PPSS1
Reset
0
0
0
0
0
0
0
Figure 4-13. Port S Polarity Select Register (PPSS)
Read: Anytime. Write: Anytime.
This register selects whether a pull-down or a pull-up device is connected to the pin.
Table 4-10. PPSS Field Descriptions
0
PPSS0
0
Field
Description
7–0
PPSS[7:0]
Pull Select Port S
0 A pull-up device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input or as wired-OR output.
1 A pull-down device is connected to the associated port S pin, if enabled by the associated bit in register PERS
and if the port is used as input.
4.3.2.7 Port S Wired-OR Mode Register (WOMS)
Module Base + 0x000E
7
R
WOMS7
W
6
WOMS6
5
WOMS5
4
WOMS4
3
WOMS3
2
WOMS2
Reset
0
0
0
0
0
0
Figure 4-14. Port S Wired-OR Mode Register (WOMS)
Read: Anytime. Write: Anytime.
1
WOMS1
0
0
WOMS0
0
This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a
multipoint connection of several serial modules. This bit has no influence on pins used as inputs.
Table 4-11. WOMS Field Descriptions
Field
Description
7–0
Wired-OR Mode Port S
WOMS[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
151