MC9S12KG128_10 Datasheet, PDF (255/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

IBC5-3
(bin)
010
011
100
101
110
111
scl2start
(clocks)
2
6
14
30
62
126
Chapter 8 Inter-Integrated Circuit (IICV2) Block Description
scl2stop
(clocks)
9
9
17
33
65
129
scl2tap
(clocks)
6
6
14
30
62
126
tap2tap
(clocks)
4
8
16
32
64
128
Table 8-4. Multiplier Factor
IBC7-6
00
01
10
11
MUL
01
02
04
RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 8-3, all subsequent tap points are separated by 2^IBC5-3 as shown in the
tap2tap column in Table 8-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 8-4.
SCL Divider
SCL
SDA
SDA Hold
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
255