MC9S12KG128_10 Datasheet, PDF (480/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 16 Debug Module (DBGV1) Block Description
16.3 Memory Map and Register Definition
A summary of the registers associated with the DBG sub-block is shown in Figure 16-3. Detailed
descriptions of the registers and bits are given in the subsections that follow.
16.3.1 Module Memory Map
Table 16-2. DBGV1 Memory Map
Address
Offset
0x0020
0x0021
0x0022
0x0023
0x0024
0x0025
0x0026
0x0027
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
0x002E
0x002F
Use
Debug Control Register (DBGC1)
Debug Status and Control Register (DBGSC)
Debug Trace Buffer Register High (DBGTBH)
Debug Trace Buffer Register Low (DBGTBL)
Debug Count Register (DBGCNT)
Debug Comparator C Extended Register (DBGCCX)
Debug Comparator C Register High (DBGCCH)
Debug Comparator C Register Low (DBGCCL)
Debug Control Register 2 (DBGC2) / (BKPCT0)
Debug Control Register 3 (DBGC3) / (BKPCT1)
Debug Comparator A Extended Register (DBGCAX) / (/BKP0X)
Debug Comparator A Register High (DBGCAH) / (BKP0H)
Debug Comparator A Register Low (DBGCAL) / (BKP0L)
Debug Comparator B Extended Register (DBGCBX) / (BKP1X)
Debug Comparator B Register High (DBGCBH) / (BKP1H)
Debug Comparator B Register Low (DBGCBL) / (BKP1L)
Access
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16.3.2 Register Descriptions
This section consists of the DBG register descriptions in address order. Most of the register bits can be
written to in either BKP or DBG mode, although they may not have any effect in one of the modes.
However, the only bits in the DBG module that can be written while the debugger is armed (ARM = 1) are
DBGEN and ARM
Name¹
0x0020
DBGC1
Bit 7
6
5
4
3
2
R
0
DBGEN
ARM TRGSEL BEGIN DBGBRK
W
1
Bit 0
CAPMOD
0x0021
R AF
BF
CF
0
DBGSC
W
TRG
= Unimplemented or Reserved
Figure 16-3. DBG Register Summary
MC9S12KG128 Data Sheet, Rev. 1.16
480
Freescale Semiconductor