MC9S12KG128_10 Datasheet, PDF (102/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
2.4.1.3.2 Data Compress Command
The data compress command is used to check Flash code integrity by compressing data from a selected
portion of the Flash block into a signature analyzer. The starting address for the data compress operation
is defined by the address written during the command write sequence. The number of consecutive word
addresses compressed is defined by the data written during the command write sequence. The number of
words that can be compressed in a single data compress operation ranges from 1 to 16,384. After launching
the data compress command, the CCIF flag in the FSTAT register will set after the data compress
operation has completed. The number of bus cycles required to execute the data compress operation is
equal to two times the number of addresses read plus 20 bus cycles as measured from the time the CBEIF
flag is cleared until the CCIF flag is set. After the CCIF flag is set, the signature generated by the data
compress operation is available in the FDATA register. The signature in the FDATA register can be
compared to the expected signature to determine the integrity of the selected data stored in the Flash block.
If the last address of the Flash block is reached during the data compress operation, data compression will
continue with the starting address of the Flash block.
NOTE
Since the FDATA register (or data buffer) is written to as part of the data
compress operation, a command write sequence is not allowed to be
buffered behind a data compress command write sequence. The CBEIF flag
will not set after launching the data compress command to indicate that a
command must not be buffered behind it. If an attempt is made to start a new
command write sequence with a data compress operation active, the
ACCERR flag in the FSTAT register will be set. A new command write
sequence must only be started after reading the signature stored in the
FDATA register. A Flash array read that generates a double bit fault will
overwrite the contents of the FDATA register.
In order to take corrective action, it is recommended that the data compress command be executed on a
Flash sector or subset of a Flash sector. If the data compress operation on a Flash sector returns an invalid
signature, the Flash sector should be erased using the sector erase command and then reprogrammed using
the program command.
NOTE
During the data compress operation, the Flash array is read with a
sense-amp margin setting that is different from the normal array read
setting. Therefore, if the data compress operation returns an invalid
signature, the section of the Flash array compressed may still be functional.
The failing section of the Flash array could be validated using normal array
read operations.
The data compress command can be used to verify that a sector or sequential set of sectors are erased.
If the ECC logic detects a double bit fault during the data compress operation, the operation will terminate
immediately and set the DFDIF and ACCERR flags in the FSTAT register. The faulty address will be
stored in the FADDR registers and the ECC parity bits read at the faulty address will be stored in the
FDATALO register. The CCIF flag will set after the DFDIF flag is set and the faulty information is stored
in the FADDR and FDATALO registers.
MC9S12KG128 Data Sheet, Rev. 1.16
102
Freescale Semiconductor