MC9S12KG128_10 Datasheet, PDF (484/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 16 Debug Module (DBGV1) Block Description
16.3.2.2 Debug Status and Control Register (DBGSC)
Module Base + 0x0021
Starting address location affected by INITRG register setting.
7
6
5
4
3
2
1
0
R
AF
BF
CF
0
W
TRG
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 16-5. Debug Status and Control Register (DBGSC)
Field
7
AF
6
BF
5
CF
3:0
TRG
Table 16-5. DBGSC Field Descriptions
Description
Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger A did not match
1 Trigger A match
Trigger B Match Flag — The BF bit indicates if trigger B match condition was met since arming.This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger B did not match
1 Trigger B match
Comparator C Match Flag — The CF bit indicates if comparator C match condition was met since arming.This
bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Comparator C did not match
1 Comparator C match
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown Table 16-6. See
Section 16.4.2.5, “Trigger Modes,” for more detail.
Table 16-6. Trigger Mode Encoding
TRG Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
↓
1111
Meaning
A only
A or B
A then B
Event only B
A then event only B
A and B (full mode)
A and Not B (full mode)
Inside range
Outside range
Reserved
(Defaults to A only)
MC9S12KG128 Data Sheet, Rev. 1.16
484
Freescale Semiconductor