MC9S12KG128_10 Datasheet, PDF (177/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 5
Clocks and Reset Generator (CRGV4) Block Description
5.1 Introduction
This specification describes the function of the clocks and reset generator (CRGV4).
5.1.1 Features
The main features of this block are:
• Phase-locked loop (PLL) frequency multiplier
— Reference divider
— Automatic bandwidth control mode for low-jitter operation
— Automatic frequency lock detector
— CPU interrupt on entry or exit from locked condition
— Self-clock mode in absence of reference clock
• System clock generator
— Clock quality check
— Clock switch for either oscillator- or PLL-based system clocks
— User selectable disabling of clocks during wait mode for reduced power consumption
• Computer operating properly (COP) watchdog timer with time-out clear window
• System reset generation from the following possible sources:
— Power-on reset
— Low voltage reset
Refer to the device overview section for availability of this feature.
— COP reset
— Loss of clock reset
— External pin reset
• Real-time interrupt (RTI)
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
177