MC9S12KG128_10 Datasheet, PDF (93/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (S12FTS128K1ECCV1)
MCU Address (0x4000-0x7FFF)
Byte Select
0 1 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
FADDR Register
0
11
1
FADDRHI[4:0]
FADDRLO[7:0]
MCU Address (0xC000-0xFFFF)
1 1 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0
Byte Select
Figure 2-16. FADDR to MCU Address Mapping (Unpaged)
2.3.2.11 Flash Data Registers (FDATA)
The FDATAHI and FDATALO registers are the Flash data registers.
Module Base + 0x000A
7
6
5
4
3
2
1
0
R
FDATAHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-17. Flash Data High Register (FDATAHI)
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
FDATALO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-18. Flash Data Low Register (FDATALO)
All FDATAHI and FDATALO bits are readable but are not writable. After an array write as part of a
command write sequence, the FDATA registers will contain the data written. At the completion of a data
compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression
signature is readable in the FDATA registers until a new command write sequence is started or a double bit
fault is detected in a Flash array read operation. If a double bit fault is detected during a Flash array read,
erase verify or data compress operation, the parity bits stored in the Flash array at the failed location will
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
93