MC9S12KG128_10 Datasheet, PDF (159/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.4.2 Port P Input Register (PTIP)
Chapter 4 Port Integration Module (PIM9KG128V1)
Module Base + 0x0019
7
R PTIP7
6
PTIP6
5
PTIP5
4
PTIP4
3
PTIP3
2
PTIP2
W
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-24. Port P Input Register (PTIP)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIP1
u
0
PTIP0
u
4.3.4.3 Port P Data Direction Register (DDRP)
Module Base + 0x001A
7
R
DDRP7
W
6
DDRP6
5
DDRP5
4
DDRP4
3
DDRP3
2
DDRP2
1
DDRP1
0
DDRP0
Reset
0
0
0
0
0
0
0
0
Figure 4-25. Port P Data Direction Register (DDRP)
Read: Anytime. Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins. The PWM
forces the I/O state to be an output for each port line associated with an enabled PWM7-0 channel. Channel
7 can force the pin to input if the shutdown feature is enabled. If a SPI module is enabled, the SPI
determines the pin direction
If the PWM, SPI1 and SPI2 functions are disabled, the corresponding Data Direction Register bit reverts
to control the I/O direction of the associated pin.
Table 4-24. DDRP Field Descriptions
Field
7–0
Data Direction Port P
DDRP[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
159