MC9S12KG128_10 Datasheet, PDF (445/606 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2) Block Description
14.3.2 Register Descriptions
The following paragraphs describe, in address order, all the VREG3V3V2 registers and their individual
bits.
14.3.2.1 VREG3V3V2 — Control Register (VREGCTRL)
The VREGCTRL register allows to separately enable features of VREG3V3V2.
Module Base + 0x0000
7
6
5
4
3
2
1
0
R
0
0
0
0
0
LVDS
LVIE
LVIF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-2. VREG3V3 — Control Register (VREGCTRL)
Table 14-3. MCCTL1 Field Descriptions
Field
2
LVDS
1
LVIE
0
LVIF
Description
Low-Voltage Detect Status Bit — This read-only status bit reflects the input voltage. Writes have no effect.
0 Input voltage V_DDA is above level V_LVID or RPM or shutdown mode.
1 Input voltage V_DDA is below level V_LVIA and FPM.
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
NOTE
On entering the reduced-power mode the LVIF is not cleared by the
VREG3V3V2.
14.4 Functional Description
Block VREG3V3V2 is a voltage regulator as depicted in Figure 14-1. The regulator functional elements
are the regulator core (REG), a low-voltage detect module (LVD), a power-on reset module (POR) and a
low-voltage reset module (LVR). There is also the regulator control block (CTRL) which represents the
interface to the digital core logic but also manages the operating modes of VREG3V3V2.
MC9S12KG128 Data Sheet, Rev. 1.16
Freescale Semiconductor
445