XRT72L13 Datasheet, PDF (89/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
B.2 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT 72L13 DS3
Framer will indicate that this data is ready to be
read by asserting the Rdy_Dtck (DTACK*) sig-
nal.
B.3 After the µC/µP detects the Rdy_Dtck signal
(from the XRT 72L13 DS3 Framer), it termi-
nates the "Read" cycle by toggling the RdB_DS
(Data Strobe) input pin "high".
For subsequent read operations, within this burst cy-
cle, the µC/µP simply repeats steps B.1 through B.3,
as illustrated in Figure 43.
FIGURE 43. BEHAVIOR THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT "READ" OPERATIONS
WITHIN THE BURST I/O CYCLE (MOTOROLA-TYPE µC/µP)
ALE_AS
A[8:0]
CS*
D[15:0]
RDB_DS
WRB_RW
Rdy_Dtck
Address of “Initial” Target Register (Offset = 0x00)
Not Valid Valid Data at Offset =0x01
Not Valid Valid Data at Offset =0x02
2.2.2.2.2.1.3 Terminating the Burst Access
Operation
The Burst I/O Access will be terminated upon the fall-
ing edge of the ALE_AS input signal. At this point the
Framer will cease to internally increment the "latched"
address value. Further, the µC/µP is now free to exe-
cute either a "Programmed I/O" access or to start an-
other "Burst Access" Operation with the XRT 72L13
DS3 Framer.
2.2.2.2.2.2 The "Motorola-Mode" Write Burst
Access
Whenever a "Motorola-type" µC/µP wishes to write
the contents of numerous registers or buffer locations
over a "contiguous" range of addresses, then it
should do the following.
a. Perform the initial "write" operation; of the burst
access.
b. Perform the remaining "write" operations, of the
burst access.
c. Terminate the burst access operation.
Each of these "operations" within the burst access
are described below.
2.2.2.2.2.2.1 The Initial Write Operation
The initial write operation of a "Motorola-type" Write
Burst Access is accomplished by executing a "Pro-
grammed I/O Write Cycle" as summarized below.
A.0 Execute a Single Ordinary (Programmed I/
O) Write cycle, as described in Steps A.1
through A.7 below.
A.1 Assert the ALE_AS (Address Strobe) input pin
by toggling it "low". This step enables the
Address Bus input drivers (within the XRT
72L13 DS3 Framer).
A.2 Place the address of the "initial" target register
or buffer location (within the Framer), on the
Address Bus input pins, A[8:0].
A.3 At the same time, the Address-Decoding cir-
cuitry (within the user's system) should assert
the CS* input pin of the Framer by toggling it
"low". This step enables further communication
between the µC/µP and the Framer Micropro-
cessor Interface block.
A.4 After allowing the data on the Address Bus pins
to settle (by waiting the appropriate "Address
Setup" time), the µC/µP should toggle the
ALE_AS input pin "high". This step causes the
Framer device to "latch" the contents of the
"Address Bus" into its own circuitry. At this
point, the "initial" address of the burst access
has now been selected.
A.5 Further, the µC/µP should indicate that this cur-
rent bus cycle is a "Write" operation by toggling
the WRB_RW (R/W*) input pin "low".
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