XRT72L13 Datasheet, PDF (308/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
ceive DS3 Framer" block to also declare an "OOF
Condition" if a P-bit error is detected in 2 of the last 5
"M-frames".
Whenever the "Receive DS3 Framer" block declares
"OOF" after being in the "In-Frame" State the follow-
ing will happen.
• The Receive DS3 Framer will assert the "RxOOF"
output pin (e.g., toggles it "high").
• Bit 4 (RxOOF) within the "Rx DS3 Configuration
and Status" Register will be set to "1" as depicted
below.
"Rx DS3 Configuration and Status" Register, (Ad-
dress = 0x10)
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Rx AIS
Rx LOS
Rx Idle
Rx OOF
Reserved
Framing on
Parity
F-Sync
Algo
M-Sync
Algo
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
• The "Receive DS3 Framer" block will also issue a
"Change in OOF Status" interrupt request, anytime
there is a change in the "OOF" status.
4.3.2.3 Forcing a Reframe via Software Com-
mand
The Framer IC permits the user to force a reframe
procedure of the "Receive DS3 Framer" block via
software command. If the user writes a "1" into Bit 0
I/O CONTROL REGISTER (ADDRESS = 0X01)
the “I/O Control” Register, as depicted below; then
the Receive DS3 Framer will be forced into the
"Frame Acquisition" Mode, (or more specifically, in the
"F-Bit Search State" per Figure 100 ). Afterwards, the
"Receive DS3 Framer" block will begin its search for
valid F-Bits. The Framer IC will also respond to this
command by asserting the "RxOOF" output pin, and
generating a "Change in OOF Status" interrupt.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable
TxLOC
LOC
Disable
RxLOC
AMI/
ZeroSup*
Unipolar/
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
4.3.2.4 Performance Monitoring of the Receive
DS3 Framer block
The user can monitor the number of framing bit errors
(M and F bits) that have been detected by the "Re-
ceive DS3 Framer" block. This is accomplished by
periodically reading the "PMON Framing Bit Error
Count" Registers (Address = 0x52 and 0x53), as de-
picted below.
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
F-Bit Error Count - High Byte
RO
RO
RO
RO
RO
RO
RO
1
0
1
0
0
0
0
BIT 0
RO
0
296