XRT72L13 Datasheet, PDF (216/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
3.3.2.19 RxDS3 FEAC Register
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Not Used
RxFEAC[5:0]
R/O
R/O
R/O
R/O
R/O
0
1
1
1
1
BIT 2
R/O
1
BIT 1
R/O
1
BIT 0
Not Used
R/O
0
This "Read/Write" register contains the latest 6-bit
FEAC code that has been "validated" by the Receive
FEAC Processor. The contents of this register will be
cleared if the previously "validated" code has been
"removed" by the FEAC Processor.
3.3.2.20 RxDS3 FEAC Interrupt Enable/Status
Register
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FEAC Valid
RxFEAC
Remove
Interrupt
Enable
RxFEAC
Remove
Interrupt
Status
RxFEAC
Valid
Interrupt
Enable
RxFEAC
Valid
Interrupt
Status
R/O
R/O
R/O
R/O
R/W
RUR
R/W
RUR
0
0
0
0
0
0
0
0
Bit 4 - FEAC Valid
This "Read Only" bit is set to "1" when an incoming
FEAC Message Code has been validated by the Re-
ceive DS3 Framer. This bit is cleared to "0" when the
FEAC code is removed.
NOTE: For more information on the role of this bit-field and
the Receive FEAC Processor, please see Section _.
Bit 3 - RxFEAC Remove Interrupt Enable
This "Read/Write" bit-field allows the user to enable/
disable the "RxFEAC Removal" interrupt. Writing a
"1" to this bit enables this interrupt. Likewise, writing
a "0" to this bit-field disables this interrupt.
NOTE: For more information on the role of this bit-field and
the Receive FEAC Processor, please see Section _.
Bit 2 - RxFEAC Remove Interrupt Status
A "1" in this "Read Only" bit-field indicates that the
last "validated" FEAC Message has now been re-
moved by the Receive FEAC Processor. The Re-
ceive FEAC Processor will remove a validated FEAC
message if 3 out of the last 10 received FEAC mes-
sages differ from the latest valid FEAC Message.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section _.
Bit 1 - RxFEAC Valid Interrupt Enable
This "Read/Write" bit-field allows the user to enable/
disable the "Rx FEAC Valid" interrupt. Writing a "1" to
this bit-field enables this interrupt. Whereas, writing a
"0" disables this interrupt. The value of this bit-field is
"0" following power up or reset.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section _.
Bit 0 - RxFEAC Valid Interrupt Status
A "1" in this "Read Only" bit-field indicates that a new-
ly received FEAC Message has been validated by the
Receive FEAC Processor.
NOTE: For more information on this bit-field and the
Receive FEAC Processor, please see Section _.
3.3.2.21 RxDS3 LAPD Control Register
204