XRT72L13 Datasheet, PDF (295/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
able) within the “Block Interrupt Enable” register (Ad-
dress = 0x04); as illustrated below.
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)
BIT 7
RxDS3/E3
Interrupt
Enable
BIT 6
BIT 5
Not Used
BIT 4
M13
Interrupt
Enable
BIT 3
BIT 2
Not Used
R/W
R/O
R/O
R/W
RO
RO
0
0
0
0
0
0
BIT 1
TxDS3/E3
Interrupt
Enable
R/W
0
BIT 0
One Second
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables the “Transmit Sec-
tion” (at the “Block Level”) for Interrupt Generation.
Conversely, setting this bit-field to “0” disables the
“Transmit Section” for interrupt generation.
What does it mean for the “Transmit Section” In-
terrupts to be “enabled” or “disabled” at the
“Block Level”?
If the “Transmit Section” is disabled (for interrupt gen-
eration) at the “Block” Level; then ALL “Transmit Sec-
tion” interrupts are disabled, independent of the “in-
terrupt enable/disable” state of the source level inter-
rupts.
If the “Transmit Section” is enabled (for interrupt gen-
eration) at the “block” level; then a given interrupt will
be enabled at the “source” level. Conversely, if the
“Transmit Section” is enabled (for interrupt genera-
tion) at the “Block” level; then a given interrupt will still
be disabled, if it is disabled at the “source” level.
As mentioned earlier, the “Transmit Section” of the
XRT72L13 Framer IC contains the following two inter-
rupts
• Completion of Transmission of FEAC Message
Interrupt.
• Completion of Transmission of LAPD Message
Interrupt.
The “Enabling/Disabling and Servicing” of each of
these interrupts is described below.
4.2.6.1.1 The “Completion of Transmission of
FEAC Message” Interrupt.
If the “Transmit Section” interrupts have been enabled
at the “Block” level, then the user can enable or dis-
able the “Completion of Transmission of a FEAC Mes-
sage” Interrupt by writing the appropriate value into
Bit 4 (Tx FEAC Interrupt Enable) within the “Transmit
DS3 FEAC Configuration & Status” Register (Address
= 0x31) as illustrated below.
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Not Used
Tx FEAC
Interrupt
Enable
TxFEAC
Interrupt
Status
TxFEAC
Enable
TxFEAC
GO
RO
RO
RO
R/W
RUR
R/W
R/W
0
0
0
X
0
0
0
BIT 0
TxFEAC
Busy
RO
0
Setting this bit-field to “1” enables the “Completion of
Transmission of a FEAC Message” Interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
4.2.6.1.2 Servicing the “Completion of Trans-
mission of a FEAC Message Interrupt
As mentioned earlier, once the user commands the
“Transmit FEAC Processor” to begin its transmission
of a FEAC Message, it will do the following.
1. It will read in the “six-bit” contents of the “Tx DS3
FEAC” Register (Address = 0x32); and encapsu-
late these 6 bits into a 16-bit data structure.
2. The Transmit FEAC Processor will then begin to
transmit this “16-bit” data structure (to the
Remote Terminal Equipment); repeatedly for 10
consecutive times.
3. Upon completion of the 10th transmission, the
XRT72L13 Framer IC will generate the “Comple-
tion of Transmission of a FEAC Message” Inter-
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