XRT72L13 Datasheet, PDF (42/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
PIN DESCRIPTIONS
PIN #
175
NAME
TxLineClk
176
REQ
177
TAOS
178
GND
TYPE
O
O
O
****
DESCRIPTION
Transmit Line Interface Clock:
This clock signal is output to the Line Interface Unit, along with the
TxPOS and TxNEG signals. The purpose of this output clock signal is
to provide the LIU with timing information that it can use to generate
the AMI pulses and deliver them over the transmission medium to the
Far-End Receiver. The user can configure the source of this clock to
be either the RxLineClk (from the Receiver portion of the Framer) or
the TxInClk input. The nominal frequency of this clock signal is
34.368 MHz.
Receive Equalization Enable/Disable Select output pin - (to be
connected to the XRT7300 DS3/E3 Line Interface Unit IC).
This output pin is intended to be connected to the REQB input pin of
the XRT7300 DS3/E3 Line Interface Unit IC. The user can control the
state of this output pin by writing a '0' or '1' to Bit 5 (REQB) within the
Line Interface Driver Register (Address = 0x80). If the user com-
mands this signal to toggle "high" then the internal Receive Equalizer
(within the XRT7300) will be disabled. Conversely, if the user com-
mands this output signal to toggle "low", then the internal Receive
Equalizer (within the XRT7300) will be enabled.
For information on the criteria that should be used when deciding
whether to bypass the equalization circuitry or not, please consult the
"XRT7300 DS3/E3 Line Interface Unit" data sheet.
Writing a "1" to Bit 5 of the Line Interface Drive Register (Address =
0x80) will cause this output pin to toggle "high". Writing a "0" to this
bit-field will cause this output pin to toggle "low".
Note: If the customer is not using the XRT7300 DS3/E3 Line Inter-
face Unit IC, then he/she can use this output pin for a variety of other
purposes.
"Transmit All Ones Signal" (TAOS) Command (for the XRT7300
Line Interface Unit IC).
This output pin is intended to be connected to the TAOS input pin of
the XR-T7300 DS3/E3 Line Interface Unit IC. The user can control
the state of this output pin by writing a '0' or '1' to Bit 4 (TAOS) of the
Line Interface Drive Register (Address = 0x80). If the user commands
this signal to toggle "high" then it will force the XRT7300 Line Interface
Unit IC to transmit an "All Ones" pattern onto the line. Conversely, if
the user commands this output signal to toggle "low" then the XR-
T7300 DS3/E3 Line Interface Unit IC will proceed to transmit data
based upon the pattern that it receives via the TxPOS and TxNEG
output pins.
Writing a "1" to Bit 4 of the Line Interface Drive Register (Address =
0x80) will cause this output pin to toggle "high". Writing a "0" to this
bit-field will cause this output pin to toggle "low".
NOTE: This output pin can be used for a variety of other purposes if
the XRT7300 DS3/E3 LIU is not used.
Ground Pin
30