XRT72L13 Datasheet, PDF (136/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13 MULTIPLEXER/FRAMER IC
REV. 1.0.6
áç
PRELIMINARY
occurred since the read of this register. A "1" in this
bit-field indicates that this interrupt has occurred
since the last read of this register.
NOTE: For more information on the LAPD Transmitter,
please see Section _.
2.3.2.50 TxDS3 M-Bit Mask Register )
TXDS3 M-BIT MASK REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
TxFEBEDat[2:0]
BIT 5
R/W
R/W
R/W
0
0
0
BIT 4
FEBE Reg
Enable
R/W
0
BIT 3
Tx Error
P-Bit
R/W
0
BIT 2
BIT 1
BIT 0
MBit Mask[2] MBit Mask[1] MBit Mask[0]
R/W
R/W
R/W
0
0
0
Bit 7 - 5: TxFEBEDat[2:0]
These three (3) "read/write" bit-fields, along with Bit 4
of this register, allows the user to configure and trans-
mit his/her choice for FEBE bits in each outgoing DS3
Frame. The user will write his/her value for the FEBE
bits into these bit-fields. The Transmit DS3 Framer
will insert these values into the FEBE bit-fields of
each outgoing DS3 Frame, once the user has written
a "1" to Bit 4 (FEBE Register Enable).
NOTE: For more information on this feature, please see
Section _.
Bit 4 - FEBE Register Enable
This "Read/Write" bit-field allows the user to config-
ure the Transmit DS3 Framer to insert the contents of
TxFEBEDat[2:0] into the FEBE bit-fields each outgo-
ing DS3 Frame.
Writing a "0" to this bit-field disables this feature (e.g.,
the Transmit DS3 Framer will transmit the internally
generated FEBE bits). Writing a "1" to this bit-field
enables this features (e.g., the internally generated
FEBE bits are overwritten by the contents of the
TxFEBEDat[2:0] bit-field).
NOTE: For more information on this feature, please see
Section _.
Bit 3 - Transmit Erred P-Bit
This "Read/Write bit-field allows the user to insert er-
rors into the P-bits of the outgoing DS3 frames (via
the Transmit DS3 Framer block). If the user enables
this feature, then the Transmit DS3 Framer will pro-
ceed to invert each and every P-bit, from its comput-
ed value, prior to transmission to the "Far-end" Termi-
nal.
Writing a "0" to this bit-field (the default condition) dis-
ables this feature (e.g., the correct P-bits are sent).
Writing a "1" to this bit-field enables this feature (e.g.,
the incorrect P-bits are sent).
NOTE: For more information on this feature, please see
Section _.
Bit 2 - 0 M-Bit Mask[2:0]
These "Read/Write" bit-fields allow the user to insert
errors in the M-bits for Test and Diagnostic purposes.
The Transmit DS3 Framer automatically performs an
XOR operation on the actual contents of the M-bit
fields to these register bit-fields. Therefore, for every
'1' that exists in these bit-fields, will result in a change
of state of the corresponding M-bit, prior to being
transmitted to the Far End Receive DS3 Framer.
If the user wishes to operate the Transmit DS3 Fram-
er in the normal mode (e.g., when no errors are being
injected into the M-bit fields of the outbound DS3
Frame), then he/she must ensure that these bit-fields
are all '0'.
2.3.2.51 Tx DS3 F-Bit Mask1 Register )
TX DS3 F-BIT MASK REGISTER - 1 (ADDRESS = 0X36)
BIT 7
RO
0
BIT 6
BIT 5
Not Used
RO
RO
0
0
BIT 4
RO
0
BIT 3
BIT 2
BIT 1
BIT 0
FBit Mask[27] FBit Mask[26] FBit Mask[25] FBit Mask[24]
R/W
R/W
R/W
R/W
0
0
0
0
Bits 3 - 0 F-Bit Mask[27:24]
These "Read/Write" bit-fields allow the user to insert
errors into the first four F-bits of a DS3 M-frame, for
test and diagnostic purposes. The Transmit DS3
Framer block (within the chip) automatically performs
an XOR operation on the actual contents of these F-
bit fields to these register bit-fields. Therefore, for ev-
ery "1" that exists in these bit-fields, this will result in a
change of state for the corresponding F-bit, prior to
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