XRT72L13 Datasheet, PDF (357/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
As M12 MUX #1 generates this DS2 signal, it will cre-
ate a data stream that has the “DS2 Framing” Struc-
ture, as presented below in Figure 121.
FIGURE 121. ILLUSTRATION OF THE DS2 FRAMING STRUCTURE
M0
I[48] C11 I[48]
F0
I[48] C12 I[48] C13 I[48]
F1
I[48]
M1
I[48] C21 I[48]
F0
I[48] C22 I[48] C23 I[48]
F1
I[48]
M1
I[48] C31 I[48]
F0
I[48] C32 I[48] C33 I[48]
F1
I[48]
X
I[48] C41 I[48]
F0
I[48] C42 I[48] C43 I[48]
F1
I[48]
Configuring the remaining M12 MUX Blocks
The remaining M12 MUX Blocks (e.g., M12 MUX
Blocks numbers 2 through 7) can also be configured
to operate in the “DS1” Mode, by setting Bits 4 (M12
G.747) and Bit 5 (M12 Bypass) to “0”, within each of
their corresponding “M12 DS2 Configuration” Regis-
ters (Address locations: 0x1B through 0x20).
5.2.1.1.1.1.1 Description of the DS2 Frames
and Associated Overhead Bits
In order to fully understand and appreciate the role
the M12 MUX block while it is operating in the “DS1”
FIGURE 122. THE DS2 PAYLOAD BITS
Mode, it is best to first describe the DS2 framing for-
mat.
The DS2 frame consists of 1176 bits, of which 24 of
these bits are overhead bits, and the remaining 1152
bits are “payload” bits. The “payload” data is format-
ted into packets of 48 bits and the overhead (OH) bits
are inserted between these payload packets. As
mentioned earlier, this DS2 data stream is created by
the M12 MUX performing bit-wise multiplexing of the
four (input) DS1 signals. As a consequence, each of
these 48-bit DS2 payload packets, consists of a re-
peating bit-wise multiplexing data stream, as illustrat-
ed below in Figure 122.
The 48 Payload Bits (in each Block)
D1
D2
D3
D4
D1
D2
D3
D4
.
.
.
.
NOTES:
1. D1 denotes that the source of data was from DS1 Channel #1
2. D2 denotes that the source of data was from DS1 Channel #2
3. D3 denotes that the source of data was from DS1 Channel #3
4. D4 denotes that the source of data was from DS1 Channel #4
Since each of the DS2 payload packets consists of 48
bits, then that means that each of the four DS1 sig-
nals, contributed 12 bits of data to this data stream.
The DS2 F and M Bits
Each DS2 frame consists of 8 F-bits and 3 M-bits.
The purpose of these F and M bits are to permit the
remote terminal equipment to acquire and maintain
DS2 frame synchronization, with this data stream.
The “F” bits are used to support “sub-frame” frame
synchronization; whereas the “M” bits are used to
support “M” frame synchronization.
The CXX Bits
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