XRT72L13 Datasheet, PDF (151/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
2.3.2.86 PMON Holding Register
PMON HOLDING REGISTER (ADDRESS = 0X6C)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
PMON Holding Value
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
Each of the PMON registers are 16 bit "Reset-upon-
Read" registers. More specifically, whenever the Mi-
croprocessor intends to read a PMON register, there
are two things to bear in mind.
1. This Microprocessor is going to require two read
accesses in order read out the full 16-bit expres-
sion of these PMON registers.
2. The entire 16-bit expression (of a given PMON
register) is going to be reset, immediately after
the Microprocessor has completed its first read
access to the PMON register.
Hence, the contents of the other byte (of the partially
read PMON register) will reside within the PMON
Holding register.
2.3.2.87 One Second Error Status Register
ONE SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
RO
0
BIT 3
RO
0
BIT 2
RO
0
BIT 1
Errored
Second
RO
0
BIT 0
Severely
Errored
Second
RO
0
Bit 1 - Errored Second
This “Read-Only” bit-field indicates whether or not
there was at least one error within the last one sec-
ond accumulation period.
If no error has occurred (within the last one second
accumulation period) then this bit-field will be set to
“0”. Conversely, if at least one error has occurred
(within the last one second accumulation period) then
this bit-field will be set to “1”.
Bit 0 - Severely Errored Second
This “Read-Only” bit-field indicates whether or not the
error-rate, in the last one second interval was greater
than 1e-3.
If the bit error rate (within the last one second accu-
mulation period) is less than 1e-3, then this bit-field
will be set to “0”. Conversely, if the bit-error rate
(within the last one second accumulation period) is
greater than 1e-3, then this bit-field will be set to “1”.
2.3.2.88 LCV One Second Accumulator Regis-
ter - MSB
LCV - ONE SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
BIT 4
BIT 3
BIT 2
LCV - One Second Count - High Byte
RO
RO
RO
RO
0
0
0
0
BIT 1
RO
0
BIT 0
RO
0
This "Read-Only" register, along with the "LCV - One
Second Accumulator Register - LSB" (Address =
0x6F) contains a 16-bit representation of the number
of "LCV (Line Code Violation) Events that have been
detected by the Receive DS3 Framer block, within the
last one-second sampling period. This register con-
tains the MSB (or Upper-Byte) value of this 16 bit ex-
pression.
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