XRT72L13 Datasheet, PDF (235/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
PMON FRAMING BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Framing Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON Framing Bit Error Count Register - MSB" (Ad-
dress = 0x52) contains a 16-bit representation of the
number of "Framing Bit Errors" that have been detect-
ed by the Receive DS3 Framer block (within the chip),
since the last read of these registers. This register
contains the LSB (or Lower-Byte) value of this 16 bit
expression.
3.3.2.65 PMON P-Bit Error Event Count Regis-
ter - MSB
PMON P-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X54)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
P-Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON P-Bit Error Count Register - LSB" (Address =
0x55) contains a 16-bit representation of the number
of "P-bit Errors that have been detected by the Re-
ceive DS3 Framer block (within the chip), since the
last read of these registers. This register contains the
MSB (or Upper-Byte) value of this 16 bit expression.
3.3.2.66 PMON P-Bit Error Event Count Regis-
ter - LSB
PMON P-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X55)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
P-Bit Error Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON P-Bit Error Count Register - MSB" (Address =
0x54) contains a 16-bit representation of the number
of "P-bit Errors that have been detected by the Re-
ceive DS3 Framer block (within the chip), since the
last read of these registers. This register contains the
LSB (or Lower-Byte) value of this 16 bit expression.
3.3.2.67 PMON FEBE Event Count Register -
MSB
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