XRT72L13 Datasheet, PDF (294/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
NOTE: The user will typically make the selection based
upon the "set-up" and "hold" time requirements of the
"Transmit LIU" IC.
FIGURE 89. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE RISING EDGE OF TXLINECLK
t32
TxLineClk
t30
t33
TxPOS
TxNEG
FIGURE 90. WAVEFORM/TIMING RELATIONSHIP BETWEEN TXLINECLK, TXPOS AND TXNEG - TXPOS AND TXNEG
ARE CONFIGURED TO BE UPDATED ON THE FALLING EDGE OF TXLINECLK
t32
TxLineClk
t31
t33
TxPOS
TxNEG
4.2.6 Transmit Section Interrupt Processing
The "Transmit Section" of the XRT72L13 can gener-
ate an interrupt to the Microcontroller/Microprocessor
for the following two reasons.
• Completion of Transmission of FEAC Message
• Completion of Transmission of LAPD Message
4.2.6.1 Enabling "Transmit Section" Interrupts
As mentioned in Section 1.6, the Interrupt Structure,
within the XRT72L13 contains two hierarchical levels:
• Block Level
• Source Level
The Block Level
The "Enable" State of the "Block" Level for the Trans-
mit Section Interrupts dictates whether or not inter-
rupts (if enabled at the source level), are actually en-
abled.
The user can enable or disable these “Transmit Sec-
tion” interrupts, at the “Block Level” by writing the ap-
propriate data into Bit 1 (“Tx DS3/E3 Interrupt En-
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