XRT72L13 Datasheet, PDF (103/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

áç
PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
Bits 6 thru 0 - RxDS2 AIS Channel [6:0]
These seven (7) “Read/Write” bit-fields permits the
user to specify which “inbound” DS2 channel (which
is demultiplexed from the inbound DS3 channel) will
carry an AIS (All Ones) pattern.
For example, setting “Bit 5” (within this register) to “1”
configures the XRT72L13 M13 device to overwrite the
contents of the de-multiplexed DS2 channel (corre-
sponding to channel 5) with the AIS (All Ones) pat-
tern.
Setting “Bit 5” to “0” configures the “Receive” DS2
Channel 5 to carry normal traffic (as de-multiplexed
from the inbound DS3 data stream).
2.3.2.14 DS3 Test Register
DS3 TEST REGISTER (ADDRESS = 0X0C)
BIT 7
Not Used
R/O
0
BIT 6
Rx Payload
Clock
Enable
R/W
0
BIT 5
Tx Payload
Clock
Enable
R/W
0
BIT 4
Rx PRBS
Lock
Indicator
R/O
0
BIT 3
Rx PRBS
Enable
R/W
0
BIT 2
Tx PRBS
Enable
R/W
0
BIT 1
Rx DS3
Bypass
R/W
0
BIT 0
Tx DS3
Bypass
R/W
0
Bit 6 - Rx Payload Clock Enable
This “Read/Write” bit-field permits the user to config-
ure the “Receive Payload Data Output Interface” (of
the XRT72L13 M13 device) to generate either (a) a
gapped-serial clock signal or (b) an ungapped-serial
clock, along with an “RxOHInd” output signal.
Setting this bit-field to “0” configures the XRT72L13 to
generate an ungapped (44.736MHz) clock sjgnal via
the “RxClk” output pin, and to pulse the “RxOHInd”
output pin, coincident with an Overhead bit being out-
put via the “RxSer” output pin.
Setting this bit-field to “1” configures the XRT72L13 to
generate a gapped clock signal (e.g., a clock edge for
each payload bit) via the “RxOHInd” output pin.
NOTE: This feature is only applicable if the XRT72L13 has
been configured to operate in the “DS3 Clear Channel
Framer” Mode.
Bit 5 - Tx Payload Clock Enable
This “Read/Write” bit-field permits the user to config-
ure the “Transmit Payload Data Input Interface” (or
the XRT72L13 M13 device) to generate either (a) a
gapped-serial clock signal or (b) an ungapped-serial
clock, along with the “TxOHInd” output signal.
Setting this bit-field to “0” configurese the XRT72L13
to accept an ungapped clock (44.736MHz) signal via
the “TxInClk” input pin (or to output an ungapped
clock signal via the “RxOutClk” output pin). Further,
in this mode, the XRT72L13 will pulse the “TxOHInd”
output pin one bit period prior to the processing of an
overhead bit.
Setting this bit-field to “1” configures the XRT72L13 to
generate a gapped clock signal (e.g., a clock edge for
each payload bit) via the “TxOHInd” output pin.
NOTE: This feature is only applicable if the XRT72L13 has
been configured to operate in the “DS3 Clear Channel
Framer” Mode.
Bit 4 - Rx PRBS Lock Indicator
This “Read-Only” bit-field indicates whether or not the
“PRBS Checker/Receiver has acquired “PRBS Lock”
with the payload portion of the “inbound” DS3 data
stream.
If this bit-field is set to “0” then the “PRBS Checker/
Receiver” has not acquired “PRBS Lock” with the
payload portion of the “inbound” DS3 data stream.
Conversely, if this bit-field is set to “1”, then the
“PRBS Checker/Receiver” has acquired “PRBS Lock”
(or Pattern Sync) with the payload portion of the “in-
bound” DS3 data stream.
NOTE: The contents of this bit-field are valid only if the
“PRBS Checker/Receiver” is enabled.
Bit 3 - Rx PRBS Enable
This “Read/Write” bit-field permits the user to enable
the “PRBS Checker/Receiver” block within the
XRT72L13 M13 device.
Setting this bit-field to “0” disables the “PRBS Check-
er/Receiver” block.
Setting this bit-field to “1” enables the “PRBS Check-
er/Receiver” block.
Bit 2 - Tx PRBS Enable
This “Read/Write” bit-field permits the user to enable
or disable the “PRBS Generator/Transmitter” block
within the XRT72L13 M13 device.
Setting this bit-field to “0” disables the “PRBS Gener-
ator/Transmitter” block.
Setting this bit-field to “1” enables the “PRBS Genera-
tor/Transmitter” block.
91