XRT72L13 Datasheet, PDF (232/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
Writing a "1" to this bit-field enables this feature (e.g.,
the incorrect P-bits are sent).
NOTE: For more information on this feature, please see
Section _.
Bit 2 - 0 M-Bit Mask[2:0]
These "Read/Write" bit-fields allow the user to insert
errors in the M-bits for Test and Diagnostic purposes.
The Transmit DS3 Framer automatically performs an
XOR operation on the actual contents of the M-bit
fields to these register bit-fields. Therefore, for every
'1' that exists in these bit-fields, will result in a change
of state of the corresponding M-bit, prior to being
transmitted to the Far End Receive DS3 Framer.
If the user wishes to operate the Transmit DS3 Fram-
er in the normal mode (e.g., when no errors are being
injected into the M-bit fields of the outbound DS3
Frame), then he/she must ensure that these bit-fields
are all '0'.
3.3.2.50 Tx DS3 F-Bit Mask1 Register
)
TX DS3 F-BIT MASK REGISTER - 1 (ADDRESS = 0X36)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Not Used
FBit Mask[27] FBit Mask[26] FBit Mask[25] FBit Mask[24]
RO
RO
RO
RO
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 3 - 0 F-Bit Mask[27:24]
These "Read/Write" bit-fields allow the user to insert
errors into the first four F-bits of a DS3 M-frame, for
test and diagnostic purposes. The Transmit DS3
Framer block (within the chip) automatically performs
an XOR operation on the actual contents of these F-
bit fields to these register bit-fields. Therefore, for ev-
ery "1" that exists in these bit-fields, this will result in a
change of state for the corresponding F-bit, prior to
being transmitted to the Far-End Receive DS3 Fram-
er.
If the user wishes to operate the Transmit DS3 Fram-
er block in the normal mode (e.g., when no errors are
being injected into these F-bit fields of the outbound
DS3 frames), then he/she must ensure that all of
these bit-fields are "0s".
3.3.2.51 TxDS3 F-Bit Mask2 Register
)
TXDS3 F-BIT MASK REGISTER - 2 (ADDRESS = 0X37)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FBit Mask[23] FBit Mask[22] FBit Mask[21] FBit Mask[20] FBit Mask[19] FBit Mask[18] FBit Mask[17] FBit Mask[16]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7 - 0 F-Bit Mask[23:16]
These "Read/Write" bit-fields allow the user to insert
errors into the fifth through twelfth F-bits of a DS3 M-
frame, for test and diagnostic purposes. The Trans-
mit DS3 Framer block automatically performs an XOR
operation on the actual contents of these F-bit fields
to these register bit-fields. Therefore, for every "1"
that exists in these bit-fields, this will result in a
change of state for the corresponding F-bit, prior to
being transmitted to the Remote Receive DS3 Fram-
er.
If the user wishes to operate the Transmit DS3 Fram-
er block in the normal mode (e.g., when no errors are
being injected into these F-bit fields of the outbound
DS3 frames), then he/she must ensure that all of
these bit-fields are "0s".
3.3.2.52 TxDS3 F-Bit Mask3 Register
220