XRT72L13 Datasheet, PDF (53/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP.
MAX. UNITS
t₂₈ “TXOH” to “TxInClk” rising edge set-up Time
0
ns
t_29A TxInClk to “TxOHEnable”
Transmit LIU Interface Timing (see Figure 8 and Figure 9)
t₃₀ Rising edge of "TxLineClk" to rising edge of
"TxPOS" or "TxNEG" output signal.
(Framer is configured to output data on "TxPOS"
and "TxNEG" on rising edge of "TxLineClk"
8
ns
0.6
ns
t₃₁ Falling edge of "TxLineClk" to rising edge of
"TxPOS" or "TxNEG"
(Framer is configured to output data via "TxPOS"
and "TxNEG" on falling edge of "TxLineClk")
0.6
ns
f_TxLineClk Period of TxLineClk clock signal
44.736
MHz
t₃₂ Period of TxLineClk
22.36
ns
Receive LIU Interface Timing (see Figure 10 and Figure 11)
t₃₈ "RxPOS" or "RxNEG" set-up time to rising edge of
0
ns
"RxLineClk".
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the rising edge of "RxLi-
neClk")
t₃₉ "RxPOS" or "RxNEG" hold time, from rising edge of 2.4
ns
"RxLineClk"
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the rising edge of "RxLi-
neClk")
t₄₀ "RxPOS" or "RxNEG" set-up time to falling edge of
0
ns
"RxLineClk".
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the falling edge of "RxLi-
neClk")
t₄₁ "RxPOS" or "RxNEG" hold time, from falling edge of 2.4
ns
"RxLineClk"
(Framer is configured to sample data on "RxPOS"
and "RxNEG" input pins, on the falling edge of "RxLi-
neClk")
Receive Payload Data Output Inteface Timing - Serial Mode Operation (See Figure 12)
t₅₀ Falling edge of RxClk to "Payload Data" (RxSer) out-
put delay
0
ns
t₅₁ Falling edge of "RxClk" to "RxFrame" output delay
1.3
ns
t₅₂ Falling edge of "RxClk" to "RxOHInd" output delay.
2.6
ns
Receive Payload Data Output Interface Timing - Nibble Mode Operation (see Figure 13)
t₅₃ Falling edge of “RxClk” to rising edge of “RxFrame”
output delay
22
ns
CONDITIONS
41