XRT72L13 Datasheet, PDF (179/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
This “Read/Write” bit-field permits the user to enable
or disable the “DS2 Far-End Receive Failure” Inter-
rupt.
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Bit 2 - DS2 RED Alarm Interrupt Enable
This “Read/Write” bit-field permits the user to enable
or disable the “DS2 RED Alarm” Interrupt.
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Bit 1 - DS2 AIS Interrupt Enable
This “Read/Write” bit-field permits the user to enable
or disable the “DS2 AIS” Interrupt.
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Bit 0 - DS2 RESV Interrupt Enable.
To be provided in the next update.
2.3.2.126 DS2 # 5 Framer Interrupt Register
DS2 # 5 FRAMER INTERRUPT ENABLE REGISTER (ADDRESS = 0XAF)
BIT 7
BIT 6
Unused
R/O
R/O
0
0
BIT 5
Change in
DS2 COFA
Interrupt
Enable
BIT 4
Change in
DS2 OOF
Interrupt
Enable
RUR
0
RUR
0
BIT 3
Change in
DS2 FERF
Interrupt
Enable
RUR
0
BIT 2
Change in
DS2 RED
Alarm
Interrupt
Enable
RUR
0
BIT 1
Change in
DS2 AIS
Interrupt
Enable
RUR
0
BIT 0
Change in
DS2
RESV
Interrupt
Enable
RUR
0
Bit 5 - Change in DS2 COFA (Change of Framing
Alignment) Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not a change in the “DS2 COFA State” has occurred
since the last read of this register.
This bit-field will be set to “1” if a change in the DS2
COFA State has occurred since the last read of this
register. Conversely, this bit-field will be set to “0” if a
change in the DS2 COFA State has NOT occurred
since the last read of this register.
Bit 4 - Change in DS2 OOF (Out-of-Frame) Inter-
rupt Status
This “Reset-upon-Read” bit-field indicates whether or
not a change in the “DS2 Out-of-Frame State” has
occurred since the last read of this register.
This bit-field will be set to “1” if a change in the DS2
OOF State has occurred since the last read of this
register. Conversely, this bit-field will be set to “0” if a
change in the DS2 OOF State has NOT occurred
since the last read of this register.
Bit 3 - Change in DS2 FERF (Far-End Receive Fail-
ure) Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not a change in the “DS2 FERF State” has occurred
since the last read of this register.
This bit-field will be set to “1” if a change in the DS2
FERF State has occurred since the last read of this
register. Conversely, this bit-field will be set to “0” if a
change in the DS2 FERF State has NOT occurred
since the last read of this register.
Bit 2 - Change in DS2 RED Alarm Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not a change in the “DS2 RED Alarm State” has oc-
curred since the last read of this register.
This bit-field will be set to “1” if a change in the DS2
RED Alarm State has occurred since the last read of
this register. Conversely, this bit-field will be set to “0”
if a change in the DS2 RED Alarm State has NOT oc-
curred since the last read of this register.
Bit 1 - Change in DS2 AIS Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not a change in the “DS2 AIS State” has occurred
since the last read of this register.
This bit-field will be set to “1” if a change in the DS2
AIS State has occurred since the last read of this reg-
ister. Conversely, this bit-field will be set to “0” if a
change in the DS2 AIS State has NOT occurred since
the last read of this register.
Bit 0 - Change in DS2 RESV Interrupt Status
To be provided in the next update.
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