XRT72L13 Datasheet, PDF (234/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
PMON LCV EVENT COUNT REGISTER - MSB (ADDRESS = 0X50)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
LCV Count - High Byte
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON LCV Event Count Register - LSB" (Address =
0x51) contains a 16-bit representation of the number
of "Line Code Violations" that have been detected by
the Receive DS3 Framer block (within the chip), since
the last read of these registers. This register contains
the MSB (or Upper-Byte) value of this 16 bit expres-
sion.
3.3.2.62 PMON LCV Event Count Register - LSB
PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LCV Count - Low Byte
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
0
This "Reset-upon-Read" register, along with the
"PMON LCV Event Count Register - LSB" (Address =
0x50) contains a 16-bit representation of the number
of "Line Code Violations" that have been detected by
the Receive DS3 Framer block (within the chip), since
the last read of these registers. This register contains
the LSB (or Lower-Byte) value of this 16 bit expres-
sion.
3.3.2.63 PMON Framing Bit Error Event Count
Register - MSB
PMON FRAMING BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X52)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Framing Bit Error Count - High Byte
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
BIT 1
RUR
0
BIT 0
RUR
0
This "Reset-upon-Read" register, along with the
"PMON Framing Bit Error Count Register - LSB" (Ad-
dress = 0x53) contains a 16-bit representation of the
number of "Framing Bit Errors" that have been de-
tected by the Receive DS3 Framer block (within the
chip), since the last read of these registers. This reg-
ister contains the MSB (or Upper-Byte) value of this
16 bit expression.
3.3.2.64 PMON Framing Bit Error Event Count
Register - LSB
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