XRT72L13 Datasheet, PDF (366/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
NOTE: The locations of the remaining “DS2 Framer Status”
register (for the remaining M12 DEMUX blocks) are at
Address locations 0xA4 through 0xA9.
5.3.1.2.1.2.3 Declaring and Clearing the DS2
FERF Condition
It a given M12 DEMUX declares a “DS2 FERF” condi-
tion, then it will do so by setting Bit 3 (DS2 FERF Sta-
tus), within the corresponding “DS2 Framer Status”
Register to “1”. An illustration of Bit 3 being set to “1”,
within the “DS2 # 1 Framer Status” Register, is pre-
sented below.
DS2 # 1 FRAMER STATUS REGISTER (ADDRESS = 0XA3)
BIT 7
BIT 6
Unused
R/O
R/O
0
0
BIT 5
DS2 COFA
Status
R/W
0
BIT 4
DS2 OOF
Status
R/W
0
BIT 3
DS2 FERF
Status
R/W
1
BIT 2
DS2 RED
Alarm
Status
R/W
0
BIT 1
DS2 AIS
Status
R/W
0
BIT 0
DS2
RESV
Status
R/W
0
NOTE: The M12 DEMUX will also generate a “Change in
DS2 FERF Condition” Interrupt, if it detects or clears the
“DS2 FERF” condition.
When the M12 DEMUX ceases to declares the “DS2
FERF” condition, then it will set this bit-field back to
“0”, in order to reflect “normal” operation.
NOTE: The locations of the remaining “DS2 Framer Status”
register (for the remaining M12 DEMUX blocks) are at
Address locations 0xA4 through 0xA9.
5.3.1.2.2 E1 (ITU-T G.747) Operation
The user can configure M12 DEMUX # 1 to operate in
the “ITU-T G.747” Mode by setting Bit 4 (M12 G.747)
to “1” and Bit 5 (M12 By-Pass) to “0”, within the “M12
DS2 # 1 Configuration” Register, as illustrated below.
M12 DS2 # 1 CONFIGURATION REGISTER (ADDRESS = 0X1A)
BIT 7
Reserved
7
R/W
X
BIT 6
Reserved
6
R/W
X
BIT 5
M12
Bypass
R/W
0
BIT 4
M12
G.747
R/W
1
BIT 3
M12
G.747 Res
R/W
X
BIT 2
M12 FERF
R/W
X
BIT 1
BIT 0
M12LBCode[1:0]
R/W
R/W
X
X
Once the user implements this configuration setting
then M12 DEMUX # 1 will be configured to operate in
the “ITU-T G.747” Mode. When M12 DEMUX # 1 is
operating in the “ITU-T G.747” Mode, then it will be
configured to accept a “G.747” data stream, from the
M23 DEMUX block, and then de-multiplex this signal
into three (3) E1 signals. M12 DEMUX # 1 will then
output this signal (via the “RxDS1Data_0” through
“RxDS1Data_2” output pins). M12 DEMUX # 2 will
output this demultiplexed data upon the rising edges
of “RxDS1Clk_0” through “RxDS1Clk_2”.
Configuring the remaining M12 DEMUX Blocks
The remaining M12 DEMUX blocks (e.g., M12 DE-
MUX Block numbers 2 thorugh 7) can also be config-
ured to operate in the “E1” Mode, by setting Bit 4
(M12 G.747) to “1” and Bit 5 (M12 Bypass) to “0”,
within each of their corresponding “M12 DS2 Configu-
ration” Registers (Address Locations: 0x1B through
0x20).
5.3.1.2.2.1 Additional Roles of the M12 DEMUX
Blocks - E1 Mode
As the M12 DEMUX block accepts the DS2 data
stream and de-multiplexes it into 3 E1 signals, the
M12 DEMUX block will also do the following.
• It will acquire and maintain “G.747” synchronization
(via the “FAS” pattern). If the M12 DEMUX were to
fail to maintain G.747 frame synchronization, then it
will declare a “G.747 OOF” condition.
• It will also detect and declare a “G.747 AIS” and
“G.747 FERF” condition.
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