XRT72L13 Datasheet, PDF (149/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13
REV. 1.0.6
2.3.2.78 PMON DS2 # 7 Framing Bit Error
Counter
PMON DS2 # 7 FRAMING BIT ERROR COUNT REGISTER (ADDRESS = 0X60)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
DS2 # 7 Framing-Bit Error Count
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This “Reset-upon Read” register contains an 8-bit
representation of the number of “F” or “M-” bit errors
that have been detected by Receive DS2 Framer # 7
(within the chip), since the last read of this register.
2.3.2.79 PMON ITU-T G.747 # 1 Parity Bit Error
Count Register
PMON ITU-T G.747 # 1 P- BIT ERROR COUNT REGISTER (ADDRESS = 0X61)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
ITU-T G.747 # 1 P-Bit Error Count
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This “Reset-upon-Read” register contains an 8-bit
representation of the number of “P” bit errors that
have been detected by Receive G.747 Framer # 1
(within the chip) since the last read of this register.
NOTE: This register is only applicable if the XRT72L13 has
been configured to operate in the ITU-T G.747 Mode.
2.3.2.80 PMON ITU-T G.747 # 2 Parity Bit Error
Count Register
PMON ITU-T G.747 # 2 P- BIT ERROR COUNT REGISTER (ADDRESS = 0X62)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
ITU-T G.747 # 2 P-Bit Error Count
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This “Reset-upon-Read” register contains an 8-bit
representation of the number of “P” bit errors that
have been detected by Receive G.747 Framer # 2
(within the chip) since the last read of this register.
NOTE: This register is only applicable if the XRT72L13 has
been configured to operate in the ITU-T G.747 Mode.
2.3.2.81 PMON ITU-T G.747 # 3 Parity Bit Error
Count Register
PMON ITU-T G.747 # 3 P- BIT ERROR COUNT REGISTER (ADDRESS = 0X63)
BIT 7
RUR
0
BIT 6
RUR
0
BIT 5
RUR
0
BIT 4
BIT 3
ITU-T G.747 # 3 P-Bit Error Count
RUR
RUR
0
0
BIT 2
RUR
0
BIT 1
RUR
0
BIT 0
RUR
0
This “Reset-upon-Read” register contains an 8-bit
representation of the number of “P” bit errors that
have been detected by Receive G.747 Framer # 3
(within the chip) since the last read of this register.
NOTE: This register is only applicable if the XRT72L13 has
been configured to operate in the ITU-T G.747 Mode.
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