XRT72L13 Datasheet, PDF (54/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
AC ELECTRICAL CHARACTERISTICS (CONT.)
Test Conditions: TA = 25(C, VCC = 3.3V + 5% unless otherwise specified
SYMBOL
PARAMETER
MIN. TYP. MAX. UNITS
t₅₄ Falling edge of “RxClk” to rising edge of “RxNib[3:0]”
output delay
22
ns
Receive Overhead Data Output Interface Timing - Method 1 - Using RxOHEnable (see )Figure 14
t_59A Falling edge of “RxOHClk” to “RxFrame” output
0
ns
t_59B Falling edge of “RxOHClk” to “RxOH” output delay
21.3 ns
Receive Overhead Data Output Interface Timing - Method 2 - Using RxOHEnable (see Figure 15)
t₆₀ Rising edge of "RxOutClk" to rising edge of
"RxOHEnable" delay.
5.5
ns
CONDITIONS
t_60A Falling edge of "RxOHFrame" to rising edge of
"RxOHEnable" delay
0
ns
t_60B “RxOH” Data Valid to rising edge of
ns
"RxOHEnable" delay
Microprocessor Interface - Intel (See Figure 16)
t₆₄ A8 - A0 Setup Time to ALE_AS Low
1
ns
t₆₅ A8 - A0 Hold Time from ALE_AS Low.
2
ns
Intel Type Read Operations (See Figure 16)
t₆₆ RDS_DS, WRB_RW Pulse Width
80
ns
t₆₇ Data Valid from RDS_DS Low.
20
ns
t₆₈ Data Bus Floating from RDS_DS High
1.0
ns
t₆₉ ALE to RD Time
20
ns
t₇₀₁ RD Time to "NOT READY" (e.g., Rdy_Dtck toggling
12
ns
"Low")
t₇₀ RD to READY Time (e.g., Rdy_Dtck toggling "high") 65
ns
Intel Type Read Burst Operations (see Figure 18)
t₇₆ Minimum Time between Read Burst Access (e.g.,
60
ns
the rising edge of RD to falling edge of RD)
Intel Type Write Operations (see Figure 17 and Figure 19)
t₇₁ Data Setup Time to WR_RW High
70
ns
t₇₂ Data Hold Time from WR_RW High
10
ns
t₇₃ High Time between Reads and/or Writes
60
ns
t₇₄ ALE to WR Time
20
ns
t₇₇ Min Time between Write Burst Access (e.g., the ris- 60
ns
ing edge of WR to the falling edge of WR)
t₇₇₀ CS Assertion to falling edge of WR_RW
40
ns
Microprocessor Interface - Motorola Read Operations (See Figure 20)
42