XRT72L13 Datasheet, PDF (231/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
header and trailer bytes (e.g., flag sequence bytes,
SAPI, CR, EA values, etc.).
• Compute the frame check sequence word (16 bit
value)
• Insert the Frame Check Sequence value into the 2
octet slot after the payload section of the Message.
• Proceed to transmit the LAPD Message Frame to
the "far end" terminal via the outgoing DS3 frames.
Writing a "1" to this bit-field start the transmission of
the LAPD Message Frame, via the LAPD Transmitter.
NOTE: For more information on the LAPD Transmitter,
please see Section _.
Bit 2 - TxDL Busy
This "Read-Only" bit-field allows the local µP to "poll"
and determine if the LAPD Transmitter has completed
its transmission of the LAPD Message frame. This
bit-field will contain a "1", if the LAPD Transmitter is
still transmitting the LAPD Message frame to the "far-
end" terminal. This bit-field will toggle to "0", once the
LAPD Transmitter has completed its transmission of
the LAPD Message frame.
NOTE: For more information on the LAPD Transmitter,
please see Section _.
Bit 1 - TxLAPD Interrupt Enable
This "Read/Write" bit-field allows the user to enable
or disable the "LAPD Message Frame Transmission
Complete" interrupt.
Writing a "0" to this bit-field disables this interrupt.
Writing a "1" to this bit-field enables this interrupt.
Bit 0 - TxLAPD Interrupt Status
This "Reset Upon Read" bit-field indicates whether or
not the "LAPD Message frame Transmission Com-
plete" interrupt has occurred since the last read of
this register. The purpose of this interrupt is to let the
local µP know that the LAPD Transmitter has com-
pleted its transmission of the LAPD Message frame
(containing the latest PMDL message); and is now
ready to transmit another LAPD Message frame.
A "0" in this bit-field indicates that the "LAPD Mes-
sage frame Transmission Complete" interrupt has not
occurred since the read of this register. A "1" in this
bit-field indicates that this interrupt has occurred
since the last read of this register.
NOTE: For more information on the LAPD Transmitter,
please see Section _.
3.3.2.49 TxDS3 M-Bit Mask Register
)
TXDS3 M-BIT MASK REGISTER (ADDRESS = 0X35)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TxFEBEDat[2:0]
FEBE Reg
Enable
Tx Error
P-Bit
MBit Mask[2] MBit Mask[1] MBit Mask[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 - 5: TxFEBEDat[2:0]
These three (3) "read/write" bit-fields, along with Bit 4
of this register, allows the user to configure and trans-
mit his/her choice for FEBE bits in each outgoing DS3
Frame. The user will write his/her value for the FEBE
bits into these bit-fields. The Transmit DS3 Framer
will insert these values into the FEBE bit-fields of
each outgoing DS3 Frame, once the user has written
a "1" to Bit 4 (FEBE Register Enable).
NOTE: For more information on this feature, please see
Section _.
Bit 4 - FEBE Register Enable
This "Read/Write" bit-field allows the user to config-
ure the Transmit DS3 Framer to insert the contents of
TxFEBEDat[2:0] into the FEBE bit-fields each outgo-
ing DS3 Frame.
Writing a "0" to this bit-field disables this feature (e.g.,
the Transmit DS3 Framer will transmit the internally
generated FEBE bits). Writing a "1" to this bit-field
enables this features (e.g., the internally generated
FEBE bits are overwritten by the contents of the
TxFEBEDat[2:0] bit-field).
NOTE: For more information on this feature, please see
Section _.
Bit 3 - Transmit Erred P-Bit
This "Read/Write bit-field allows the user to insert er-
rors into the P-bits of the outgoing DS3 frames (via
the Transmit DS3 Framer block). If the user enables
this feature, then the Transmit DS3 Framer will pro-
ceed to invert each and every P-bit, from its comput-
ed value, prior to transmission to the "Far-end" Termi-
nal.
Writing a "0" to this bit-field (the default condition) dis-
ables this feature (e.g., the correct P-bits are sent).
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