XRT72L13 Datasheet, PDF (11/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

áç
PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
FIGURATION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ............ 274
TABLE 25: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (TX LOS) WITHIN THE TX DS3 CONFIGURA-
TION REGISTER, AND THE RESULTING TRANSMIT DS3 FRAMER BLOCK'S ACTION ....................... 274
TX DS3 M-BIT MASK REGISTER, ADDRESS = 0X35 .................................................................................. 275
TX DS3 F-BIT MASK1 REGISTER, ADDRESS = 0X36 ................................................................................. 275
TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37 ................................................................................. 276
TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38 ................................................................................. 276
TX DS3 F-BIT MASK4 REGISTER, ADDRESS = 0X39 ................................................................................. 276
4.2.5 The Transmit DS3 Line Interface Block ............................................................................................. 276
Figure 84. Approach to Interfacing the XRT72L13 Framer IC device to the XRT7300 DS3/E3/STS-1
Transmitter LIU .................................................................................................................... 277
Figure 85. A Simple Illustration of the "Transmit DS3 LIU Interface" block .................................. 278
Figure 86. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit
DS3 LIU Interface is operating in the Unipolar Mode ....................................................... 278
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................. 279
TABLE 26: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR*) WITHIN THE UNI I/O
CONTROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE ........... 279
Figure 87. Illustration of AMI Line Code ........................................................................................... 280
Figure 88. Illustration of two examples of B3ZS Encoding ............................................................. 280
I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................. 281
TABLE 27: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE "I/O CONTROL" REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK ............... 281
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................ 281
TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE "I/O CONTROL"
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ....... 281
Figure 89. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and Tx-
NEG are configured to be updated on the rising edge of TxLineClk ............................. 282
Figure 90. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and Tx-
NEG are configured to be updated on the falling edge of TxLineClk ............................. 282
4.2.6 Transmit Section Interrupt Processing ............................................................................................... 282
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ........................................................................ 283
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) ..................................... 283
TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) ..................................... 284
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 284
TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 285
4.3 THE RECEIVE SECTION OF THE XRT72L13 (DS3 MODE OPERATION) .............................................................. 285
Figure 91. A Simple Illustration of the Receive Section of the XRT72L13, when it has been config-
ured to operate in the DS3 Mode ....................................................................................... 286
4.3.1 The Receive DS3 LIU Interface Block ............................................................................................... 286
Figure 92. A Simple Illustration of the "Receive DS3 LIU Interface" Block ................................... 287
Figure 93. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar
Data ...................................................................................................................................... 288
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................ 288
TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE "I/O CONTROL"
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ....... 288
Figure 94. Illustration on how the Receive DS3 Framer (within the XRT72L13 Framer IC) being inter-
face to theXRT7300 Line Interface Unit, while the Framer is operating in Bipolar Mode ....
289
Figure 95. Illustration of AMI Line Code ........................................................................................... 289
Figure 96. Illustration of two examples of B3ZS Decoding ............................................................. 290
II/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................ 291
TABLE 30: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL .................................................... 291
Figure 97. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS
and RxNEG are to be sampled on the rising edge of RxLineClk .................................... 291
IX