XRT72L13 Datasheet, PDF (309/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53)
BIT 7
RO
0
BIT 6
RO
0
BIT 5
RO
0
BIT 4
BIT 3
F-Bit Error Count - Low Byte
RO
RO
0
0
BIT2
RO
0
BIT 1
RO
0
BIT 0
RO
0
When the µP/µC reads these registers, it will read in
the number of framing bit errors that have been de-
tected since the last read of these two registers.
These registers are reset upon read.
4.3.2.5 DS3 Receive Alarms
The Receive DS3 Framer block is capable of detect-
ing any of the following alarm conditions.
• LOS (Loss of Signal)
• AIS (Alarm Indication Signal)
• The "Idle Pattern".
• FERF (Far-End Receive Failure) of "Yellow Alarm"
condition.
• FEBE (Far-End-Block Error)
• Change in AIC State
The methods by which the "Receive DS3 Framer"
block uses to detect and declare each of these alarm
conditions are described below.
4.3.2.5.1 The Loss of Signal (LOS) Alarm
The "Receive DS3 Framer" block will declare a "Loss
of Signal" (LOS) state when it detects 180 consecu-
tive incoming "0s" via the "RxPOS" and "RxNEG" in-
put pins or if the "RLOS" input pin (from the XRT7300
DS3 LIU or the XRT7295 Line Receiver IC) is assert-
ed (e.g., driven “high”). The "Receive DS3 Framer"
block will indicate the occurrence of an LOS condition
by:
1. Asserting the RxLOS output pin (e.g., toggles it
"high").
2. Setting Bit 6 (RxLOS) within the "Rx DS3 Config-
uration and Status" Register to "1", as depicted
below.
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
Rx AIS
R/O
0
BIT 6
Rx LOS
R/O
1
BIT 5
Rx Idle
R/O
0
BIT 4
Rx OOF
R/O
1
BIT 3
Int LOS
Disable
R/W
x
BIT2
Framing on
Parity
R/W
x
BIT 1
BIT 0
F-Sync Algo M-Sync Algo
R/W
R/W
x
x
3. The "Receive DS3 Framer" block will generate a
"Change in LOS Status" interrupt request. (Note:
The Receive DS3 Framer will also declare an
"OOF" condition and perform all of the "notifica-
tion procedures" as described in Section 3.3.2.2).
4. Force the "on-chip" Transmit Section to transmit a
"FERF" (Far-End Receive Failure) indicator back
out to the remote terminal.
The "Receive DS3 Framer" block will clear the "LOS"
condition when at least 60 out of 180 consecutive re-
ceived bits are "1".
NOTE: The "Receive DS3 Framer" block will also generate
the "Change in LOS Condition" interrupt, when it clears the
LOS Condition.
The Framer chip allows the user to modify the "LOS
Declaration criteria" such that an LOS condition is de-
clared only if the "RLOS" input pin (from the XRT7300
DS3/E3/STS-1 LIU IC) is asserted. In this case, the
"internally-generated" LOS criteria of "180 consecu-
tive 0s" will be disabled. The user can accomplish
this by writing a "1" to bit 3 (Int LOS Disable) of the Rx
DS3 Configuration and Status Register, as depicted
below.
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