|
XRT72L13 Datasheet, PDF (356/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC | |||
|
◁ |
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
either the DS1, the E1 (or ITU-T G.747) or the âDS2
Pass-Thruâ Modes.
5.2.1.1.1.1 Configuring M12 MUX # 1 into the
DS1 Mode
The user can configure M12 MUX # 1 to operate in
the âDS1â Mode by setting Bits 4 (M12 G.747) and 5
(M12 By-Pass) to â0â, within the âM12 DS2 # 1 Con-
figurationâ Register, as illustrated below.
M12 DS2 # 1 CONFIGURATION REGISTER (ADDRESS = 0X1A)
BIT 7
Reserved
7
R/W
X
BIT 6
Reserved
6
R/W
X
BIT 5
M12
Bypass
R/W
0
BIT 4
M12
G.747
R/W
0
BIT 3
M12
G.747 Res
R/W
X
BIT 2
M12 FERF
R/W
X
BIT 1
BIT 0
M12LBCode[1:0]
R/W
R/W
X
X
Once the user implements this configuration setting
then M12 MUX # 1 will be configured to operate in the
DS1â Mode. When M12 MUX # 1 is operating in the
âDS1â Mode, then it will be configured to accept four
(4) DS1 signals (via the âTxDS1Data_0â through
âTxDS1Data_3â input pin) and generate a DS2 signal.
M12 MUX # 1 will use the rising edges of
âTxDS1Clk_0â through âTxDS1Clk_3â in order to latch
the contents of the âTxDS1Data[3:0] inputs into the
M12 MUX # 1 circuitry.
NOTE: Once the user configures M12 MUX #1 to operate in
the âDS1â Mode, M12 DEMUX # 1 will also be configured to
operate in the âDS1â Mode.
Figure 120 presents a simple illustration of M12 MUX
# 1 (which has been configured to operate in the
âDS1â Mode), accepting the four DS1 signals, along
with their corresponding clock signals.
FIGURE 120. ILLUSTRATION OF M12 MUX #1 BEING CONFIGURED TO OPERATE IN THE âDS1â MODE
DS1 Channel 1
DS1 Channel 2
DS1 Channel 3
DS1 Channel 4
M12
MUX
DS2 Channel
As M12 MUX # 1 accepts these four (4) DS1 signals, multiplexing each of these composite DS1 signals.
it will form a âDS2â signal, by performing âbit-wiseâ
344
|
▷ |