XRT72L13 Datasheet, PDF (4/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
Mode ....................................................................................................................................... 58
1.2 XRT72L13 OPERATION WHILE IN THE "CLEAR CHANNEL DS3 FRAMER MODE" ................................ 58
Figure 29. Functional Block diagram of the XRT72L13 M13 Multiplexer/Framer IC, while Operating
in the “Clear Channel DS3 Framer Mode” ........................................................................... 59
1.2.1 Operation of the XRT72L13 while in the "Clear Channel DS3 Framer Mode" ..................................... 59
Figure 30. Illustration of the XRT72L13 M13 Multiplexer/Framer operating in the "Clear Channel DS3
Framer Local Loop-back" Mode ........................................................................................... 60
Figure 31. Illustration of the XRT72L13 M13 Multiplexer/Framer operating in the "Clear Channel DS3
Framer Remote Loop-back" Mode ....................................................................................... 61
1.3 XRT72L13 OPERATION WHILE IN THE "HIGH SPEED HDLC CONTROLLER" MODE ............................. 61
Figure 32. Illustration of the XRT72L13 M13 Multiplexer/Framer IC, when it has been configured to
operate in the "High Speed HDLC Controller" Mode ......................................................... 62
2.0 The Microprocessor Interface Block .............................................................................................. 62
Figure 33. Simple Block Diagram of the Microprocessor Interface Block, within the Framer IC .. 63
2.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL ........................................................................................... 63
TABLE 1: DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH
THE "INTEL" AND "MOTOROLA" MODES ...................................................................................... 64
TABLE 2: PIN DESCRIPTION OF MICROPROCESSOR INTERFACE SIGNALS - WHILE THE MICROPROCESSOR INTER-
FACE IS OPERATING IN THE INTEL MODE ..................................................................................... 64
TABLE 3: PIN DESCRIPTION OF THE MICROPROCESSOR INTERFACE SIGNALS WHILE THE MICROPROCESSOR IN-
TERFACE IS OPERATING IN THE MOTOROLA MODE ...................................................................... 65
2.2 INTERFACING THE XRT 72L13 DS3 FRAMER TO THE LOCAL µC/µP OVER VIA THE MICROPROCESSOR INTERFACE
BLOCK 65
2.2.1 Interfacing the XRT 72L13 DS3 Framer to the Microprocessor over an 8 bit wide bi-directional Data Bus
65
2.2.2 Data Access Modes ............................................................................................................................. 66
Figure 34. Behavior of Microprocessor Interface signals during an "Intel-type" Programmed I/O
Read Operation ...................................................................................................................... 67
Figure 35. Behavior of the Microprocessor Interface Signals, during an "Intel-type" Programmed I/
O Write Operation .................................................................................................................. 68
Figure 36. Illustration of the Behavior of Microprocessor Interface signals, during a "Motorola-type"
Programmed I/O Read Operation ......................................................................................... 69
Figure 37. Illustration of the Behavior of the Microprocessor Interface signal, during a "Motorola-
type" Programmed I/O Write Operation ............................................................................... 70
Figure 38. Behavior of the Microprocessor Interface Signals, during the "Initial" Read Operation of
a Burst Cycle (Intel Type Processor) ................................................................................... 72
Figure 39. Behavior of the Microprocessor Interface Signals, during subsequent "Read" Operations
within the Burst I/O Cycle ..................................................................................................... 73
Figure 40. Behavior of the Microprocessor Interface signals, during the "Initial" Write Operation of
a Burst Cycle (Intel-type Processor) .................................................................................... 74
Figure 41. Behavior of the Microprocessor Interface Signals, during subsequent "Write" Operations
within the Burst I/O Cycle ..................................................................................................... 75
Figure 42. Behavior of the Microprocessor Interface Signals, during the "Initial" Read Operation of
a Burst Cycle (Motorola Type Processor) ........................................................................... 76
Figure 43. Behavior the Microprocessor Interface Signals, during subsequent "Read" Operations
within the Burst I/O Cycle (Motorola-type µC/µP) ............................................................... 77
Figure 44. Behavior of the Microprocessor Interface signals, during the "Initial" Write Operation of
a Burst Cycle (Motorola-type Processor) ............................................................................ 78
Figure 45. Behavior of the Microprocessor Interface Signals, during subsequent "Write" Operations
with the Burst I/O Cycle (Motorola-type µC/µP) .................................................................. 79
2.3 ON-CHIP REGISTER ORGANIZATION .................................................................................................................. 79
2.3.1 Framer Register Addressing ................................................................................................................ 79
2.3.2 M13 Mux/Framer Register Description ................................................................................................. 79
TABLE 4: REGISTER ADDRESS MAP ........................................................................................................... 80
OPERATING MODE REGISTER (ADDRESS = 0X00) ........................................................................................ 83
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