XRT72L13 Datasheet, PDF (200/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
point, the "initial" address of the burst access
has now been selected.
A.5 Further, the µC/µP should indicate that this cur-
rent bus cycle is a "Write" operation by toggling
the WR_RW (R/W*) input pin "low".
A.6 The µC/µP should then place the byte or word
that it intends to write into the "target" register,
on the bi-directional data bus, D[7:0].
A.7 Next, the µC/µP should initiate the bus cycle by
toggling the Rd_DS (Data Strobe) input pin
"low". When the XRT72L13 DS3 Framer
senses that the WR_RW input pin is "low", and
that the Rd_DS input pin has toggled "low" it
will enable the "input drivers" of the bi-direc-
tional data bus, D[7:0].
A.8 After waiting the appropriate amount of time, for
this newly placed data to settle on the bi-direc-
tional data bus( e.g., the "Data Setup" time) the
Framer will assert the Rdy_Dtck (DTACK) out-
put signal.
A.9 After the µP/µC detects the Rdy_Dtck signal
(from the Framer) it should toggle the Rd_DS
input pin "high". This action accomplishes two
things:
a. It latches the contents of the bi-directional data
bus into the XRT72L13 DS3 Framer Microproces-
sor Interface block.
b. It terminates the "Write" cycle.
Figure 57 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
during the "Initial" write operation within a Burst Ac-
cess, for a "Motorola-type" µC/µP.
FIGURE 57. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE "INITIAL" WRITE OPERATION
OF A BURST CYCLE (MOTOROLA-TYPE PROCESSOR)
ALE_AS
A[8:0]
CS*
D[15:0]
RDB_DS
Address of “Initial” Target Register (Offset = 0x00)
Data to be Written (Offset = 0x00)
Rdy_Dtck
At the completion of this initial write cycle, the µC/µP
has written a byte or word into the first register or
buffer location (within the XRT72L13 DS3 Framer) for
this particular burst I/O access. In order to illustrate
how this "burst I/O cycle" works, the byte (or word) of
data, that is being written in Figure 57 has been la-
beled "Data to be Written (Offset = 0x00)."
3.2.2.2.2.2.2 The Subsequent Write Operations
The procedure that the µC/µP must use to perform
the remaining write cycles, within this burst access
operation, is presented below.
B.0 Execute each subsequent write cycle, as
described in Steps B.1 through B.3
B.1 Without toggling the ALE_AS (Address Strobe)
input pin (e.g., keeping it "high"); apply the
value of the next byte or word (to be written into
the Framer) to the bi-directional data bus pins,
D[7:0].
B.2 Toggle the Rd_DS (Data Strobe) input pin
"low". This step accomplishes the following.
a. The Framer internally increments the "latched
address" value (within the Microprocessor Inter-
face).
b. The input drivers of the bi-directional data bus are
enabled.
NOTE: In order to insure that the XRT72L13 DS3 Framer
will interpret this signal as being a "Write" signal, the µC/
µP should keep the WR_RW input pin "low".
B.3 After some settling time, the data, in the inter-
nal data bus, will stabilize and is ready to be
latched into the Framer Microprocessor Inter-
face block. The Microprocessor Interface block
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