XRT72L13 Datasheet, PDF (302/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
4.3.1.2.2 B3ZS Decoding
The Transmit DS3 LIU Interface block and the associ-
ated LIU embed and combine the data and clocking
information into the line signal that is transmitted to
the remote terminal equipment. The "remote termi-
nal" equipment has the task of recovering this data
and timing information from the incoming DS3 data
stream. Most clock and data recovery schemes rely
on the use of Phase-Locked-Loop technology. One of
the problems of using Phase-Locked-Loop (PLL)
technology for clock recovery is that it relies on transi-
tions in the line signal, in order to maintain “lock” with
the incoming DS3 data-stream. Therefore, these
clock recovery scheme, are vulnerable to the occur-
rence of a long stream of consecutive zeros (e.g., no
transitions in the line). This scenario can cause the
PLL to lose "lock" with the incoming DS3 data, there-
by causing the "clock" and data recovery process of
the receiver to fail. Therefore, some approach is
needed to insure that such a long string of consecu-
tive zeros can never happen. One such technique is
B3ZS (or Bipolar 3 Zero Substitution) encoding.
In general the B3ZS line code behaves just like AMI;
with the exception of the case when a long string of
consecutive zeros occurs on the line. Any 3 consecu-
tive zeros will be replaced with either a "00V" or a
"B0V" where "B" refers to a Bipolar pulse (e.g., a
pulse with a polarity that is compliant with the alter-
nating polarity scheme of the AMI coding rule). And
"V" refers to a Bipolar Violation pulse (e.g., a pulse
with a polarity that violates the alternating polarity
scheme of AMI.) The decision between inserting an
"00V" or a "B0V" is made to insure that an odd num-
ber of Bipolar (B) pulses exist between any two Bipo-
lar Violation (V) pulses. The Receive DS3 Framer,
when operating with the B3ZS Line Code is responsi-
ble for decoding the B3ZS-encoded data back into a
unipolar (binary-format). For instance, if the Receive
DS3 Framer detects a "00V" or a "B0V" pattern in the
incoming pattern, the Receive DS3 Framer will re-
place it with three consecutive zeros. Figure 96 pre-
sents a timing diagram that illustrates examples of
B3ZS decoding.
FIGURE 96. ILLUSTRATION OF TWO EXAMPLES OF B3ZS DECODING
Data 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1
00 V
Line Signal
RxPOS
RxNEG
B 0V
4.3.1.2.3 Line Code Violations
The "Receive DS3 LIU Interface" block will also check
the incoming DS3 data stream for line code viola-
tions. For example, when the Receive DS3 LIU Inter-
face block detects a valid bipolar violation (e.g., in
B3ZS line code), it will substitute three zeros into the
binary data stream. However, if the bipolar violation
is invalid, then an LCV (Line Code Violation) is
flagged and the "PMON LCV Event Count" Register
(Address = 0x50 and 0x51) will also be incremented.
Additionally, the "LCV-One Second Accumulation"
Registers (Address = 0x6E and 0x6F) will be incre-
mented. For example: If the incoming DS3 data is
B3ZS encoded, the Receive DS3 LIU Interface block
will also increment the "LCV One Second Accumula-
tion" Register if three (or more) consecutive zeros are
received.
4.3.1.2.4 RxLineClk Clock Edge Selection
The incoming unipolar or bipolar data, applied to the
RxPOS and the RxNEG input pins are clocked into
the Receive DS3 LIU Interface block via the RxLi-
neClk signal. The Framer IC allows the user to spec-
ify which edge (e.g, rising or falling) of the RxLineClk
signal will sample and latch the signal at the RxPOS
and RxNEG input signals into the Framer IC. This
feature was included in the XRT72L13 design in order
to insure that the user can always meet the “RxPOS”
and “RxNEG” to “RxLineClk” set-up and hold time re-
quirements. The user can make this selection by
writing the appropriate data to bit 1 of the "I/O Con-
trol" Register, as depicted below.
290