XRT72L13 Datasheet, PDF (84/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13 MULTIPLEXER/FRAMER IC
REV. 1.0.6
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PRELIMINARY
FIGURE 38. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE "INITIAL" READ OPERATION
OF A BURST CYCLE (INTEL TYPE PROCESSOR)
ALE_AS
A[8:0]
CS*
D[15:0]
RDB_DS
WRB_RW
Rdy_Dtck
Address of “Initial” Target Register (Offset = 0x00)
Not Valid
Valid Data of Offset = 0x00
At the completion of this initial read cycle, the µC/µP
has read in the contents of the first register or buffer
location (within the XRT 72L13 DS3 Framer) for this
particular burst I/O access operation. In order to illus-
trate how this "burst access operation" works, the
byte (or word) of data, that is being read in Figure 38,
has been labeled "Valid Data at Offset = 0x00". This
label indicates that the µC/µP is reading the very first
register (or buffer location) in this burst access opera-
tion.
2.2.2.2.1.1.2 The Subsequent Read Operations
The procedure that the µC/µP must use to perform
the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycles, as
described in steps 1 through 3 below.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "low"); toggle the RdB_DS input pin
"low". This step accomplishes the following.
a. The Framer will internally increments the "latched
address" value (within the Microprocessor Inter-
face circuitry).
b. The output drivers of the "bi-directional" data bus,
D[7:0] are enabled. At some time later, the regis-
ter or buffer location corresponding to the "incre-
mented" latched address value will be driven onto
the bi-directional data bus.
B.2 Immediately after the "Read Strobe" pin toggles
"low" the Framer IC will toggle the Rdy_Dtck
(READY) output pin "low" to indicate its "NOT
READY" status.
B.3 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT 72L13 DS3
Framer will indicate that this data is ready to be
read by toggling the Rdy_Dtck (READY) signal
"high".
B.4 After the µC/µP detects the Rdy_Dtck signal
(from the XRT 72L13 DS3 Framer), it can then
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