XRT72L13 Datasheet, PDF (30/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
PIN DESCRIPTIONS
PIN #
99
NAME
TxDS1Clk_25
100
TxDS1Data_24/
TxHDLCData_4
101
TxDS1Clk_24
102
TxDS1Data_23/
TxHDLCData_3
TYPE
I
I
I
I
DESCRIPTION
Transmit DS1/E1 Clock Input - Channel 25:
This input pin accepts either a DS1 (1.544MHz) or an E1 (2.048MHz)
clock signal from the Terminal Equipment. The falling edge of this sig-
nal is used to sample the data at the "TxDS1Data_25" input pin.
Transmit DS1/E1 Data Input - Channel 24/Transmit HDLC Control-
ler Block Input - Bit 4:
The funtion of this output pin depends upon whether the XRT72L13 is
operating in the "Multiplexer/De-Multiplexer" Mode or in the "High
Speed HDLC Controller" Mode.
Transmit DS1/E1 Data Input - Channel 24 (Multiplexer/De-Multi-
plexer Mode):
This input pin accepts either a DS1 or E1 signal from the Terminal
Equipment. This input pin is sampled upon the "falling edge" of the
TxDS1Clk_24 signal.
Transmit HDLC Controller Block Input - Bit 4: (High Speed HDLC
Controller Mode)
This input pin, along with TxHDLC_Data[0:3] and TxHDLC_Data[5:7]
function as the "Transmit HDLC Controller Byte input interface. Data
that resides on this bus, during the rising edge of "TxHDLCClk" is
latched into the "Transmit HDLC Controller Block" and will be encap-
sulated into a HDLC frame and transmitted to the remote terminal
equipment.
Transmit DS1/E1 Clock Input - Channel 24:
This input pin accepts either a DS1 (1.544MHz) or an E1 (2.048MHz)
clock signal from the Terminal Equipment. The falling edge of this sig-
nal is used to sample the data at the "TxDS1Data_24" input pin.
Transmit DS1 Data Input - Channel 23/Transmit HDLC Controller
Block Input - Bit 3:
The funtion of this output pin depends upon whether the XRT72L13 is
operating in the "Multiplexer/De-Multiplexer" Mode or in the "High
Speed HDLC Controller" Mode.
Transmit DS1 Data Input - Channel 23 (Multiplexer/De-Multiplexer
Mode):
This input pin accepts a DS1 signal from the Terminal Equipment.
This input pin is sampled upon the "falling edge" of the TxDS1Clk_1
signal.
NOTES:
1. This input pin is inactive if the corresponding M12 MUX is
multiplexing 3 E1's into an ITU-T G.747 data stream.
2. This input pin accepts DS2 data if M12 MUX # 6 is bypassed.
Transmit HDLC Controller Block Input - Bit 3: (High Speed HDLC
Controller Mode)
This input pin, along with TxHDLC_Data[0:2] and TxHDLC_Data[4:7]
function as the "Transmit HDLC Controller Byte input interface. Data
that resides on this bus, during the rising edge of "TxHDLCClk" is
latched into the "Transmit HDLC Controller Block" and will be encap-
sulated into a HDLC frame and transmitted to the remote terminal
equipment.
18