XRT72L13 Datasheet, PDF (293/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
I/O CONTROL REGISTER (ADDRESS = 0X01)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable
TxLOC
LOC
Disable AMI/ZeroSup* Unipolar/
RxLOC
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
0
0
Table 27 relates the content of this bit-field to the Bi-
polar Line Code that DS3 Data will be transmitted and
received at.
TABLE 27: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE "I/O CONTROL" REGISTER AND THE
BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK
BIT 4
0
1
BIPOLAR LINE CODE
B3ZS
AMI
NOTES:
1. This bit is ignored if the "Unipolar" mode is
selected.
2. This selection also effects the operation of the
"Receive DS3 LIU Interface" block
4.2.5.2 TxLineClk Clock Edge Selection
The Framer also allows the user to specify whether
the DS3 output data (via TxPOS and/or TxNEG out-
II/O CONTROL REGISTER (ADDRESS = 0X01)
put pins) is to be updated on the rising or falling edg-
es of the TxLineClk signal. The purpose of this fea-
ture is to insure that the Framer will alway be able to
output data to the LIU IC, in such a way that the LIU
set-up and hold time requirements can always be
met. This selection is made by writing to bit 2 of the
"I/O Control" Register, as depicted below.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Disable
TxLOC
LOC
Disable AMI/ZeroSup* Unipolar/
RxLOC
Bipolar*
TxLine CLK RxLine CLK
Invert
Invert
Reframe
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
X
X
0
Table 28 relates the contents of this bit field to the
clock edge of TxClk that DS3 Data is output on the
TxPOS and/or TxNEG output pins.
TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE "I/O CONTROL"
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON
BIT 2
0
1
RESULT
Rising Edge:
Outputs on TxPOS and/or TxNEG are updated on the rising edge of TxLineClk.
See Figure 89 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
Falling Edge:
Outputs on TxPOS and/or TxNEG are updated on the falling edge of TxLineClk.
See Figure 90 for timing relationship between TxLineClk, TxPOS and TxNEG signals, for this selection.
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