XRT72L13 Datasheet, PDF (348/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
BIT 2
AIC
Interrupt
Enable
R/W
0
BIT 1
OOF
Interrupt
Enable
R/W
0
BIT 0
P-Bit Error
Interrupt
Enable
R/W
0
Setting this bit-field to “1” enables this interrupt. Con-
versely, setting this bit-field to “0” disables this inter-
rupt.
Servicing the “Detection of P-Bit Error” Interrupt
Whenever the XRT72L13 Framer IC detects this in-
terrupt, it will do all of the following.
• It will assert the “Interrupt Request” output pin
(INT*) by driving it “HIGH”.
• It will set Bit 0 (P-Bit Error Interrupt Status) within
the “Rx DS3 Interrupt Status” Register, to “1”, as
indicated below.
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP-Bit Error
Interrupt
Status
LOS
Interrupt
Status
AIS
Interrupt
Status
Idle Interrupt
Status
FERF
Interrupt
Status
AIC
Interrupt
Status
OOF
Interrupt
Status
P-Bit Error
Interrupt
Status
RUR
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
0
0
0
0
0
0
1
Whenever the “Terminal Equipment” encounters the
“Detection of P-bit Error” Interrupt, it should do the fol-
lowing.
• It should read contents of “PMON Parity Error
Count” Register (located at 0x54 and 0x55), in
order to determine the number of P-bit errors
recently received.
4.3.6.2.8 The “Detection of CP-Bit Error” Inter-
rupt
If the “Detection of CP-Bit Error” Interrupt is enabled,
then the XRT72L13 Framer IC will generate an inter-
rupt, anytime the “Receive DS3 Framer” block has
detected a CP-bit error, within the “incoming” DS3 da-
ta stream.
Enabling and Disabling the “Detection of CP-Bit
Error” Interrupt:
The user can enable or disable the “Detection of CP-
Bit Error” Interrupt, by writing the appropriate value
into Bit 7 (CP-Bit Error Interrupt Enable) within the
“RxDS3 Interrupt Enable” Register, as illustrated be-
low.
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CP Bit Error
Interrupt
Enable
LOS
Interrupt
Enable
AIS
Interrupt
Enable
Idle Interrupt
Enable
FERF
Interrupt
Enable
AIC
Interrupt
Enable
OOF
Interrupt
Enable
P-Bit Error
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Setting this bit-field to “1” enables this interrupt. Con- rupt.
versely, setting this bit-field to “0” disables this inter-
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