XRT72L13 Datasheet, PDF (312/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Cp Bit Error LOS Interrupt AIS Interrupt
Interrupt
Status
Status
Status
IDLE Inter-
rupt Status
FERF Inter- AIC Interrupt
rupt Status
Status
OOF Inter-
rupt Status
P-Bit Inter-
rupt Status
RO
RUR
RUR
RUR
RUR
RUR
RUR
RUR
0
X
X
X
1
X
X
X
The Receive DS3 Framer block will clear the "FERF"
condition, when it starts to receive Receive DS3
Frames that have its "X" bits set to "1".
NOTE: The "FERF" indicator is frequently referred to as the
"Yellow Alarm".
4.3.2.5.5 The Detection of the FEBE Events
As described in Section 3.2.4.2.1.9, a given Terminal
Equipment will set the three FEBE (Far-End Block Er-
ror) bit-fields to the value [1, 1, 1] (e.g., all of the
FEBE bits are set to “1”) within the “outbound” DS3
frames; if all of the following conditions are true about
the “incoming” DS3 line signal.
• The Receive Circuitry (within the Terminal Equip-
ment) detects no P-Bit Errors.
• The Receive Circuitry (within the Terminal Equip-
ment) detects no CP-Bit Errors.
If the Receive Section of the Terminal Equipment de-
tects any P or CP bit errors, then the Transmit Section
of the Terminal Equipment will set the three FEBE
bits (within the “outbound” DS3 data stream) to a val-
ue other than [1, 1, 1].
How does the Receive DS3 Framer block (within the
XRT72L13) respond when it receives a DS3 frame
with all three (3) of its FEBE bit-fields set to “1”?
As mentioned above, the Terminal Equipment will
transmit DS3 frames, with the FEBE bits set to [1, 1,
1], during un-erred conditions. Hence, if the “Receive
DS3 Framer” block (within the XRT72L13 Framer IC)
receives DS3 frames with the FEBE bits set to [1, 1,
1] it will interpret this event as an un-erred event, and
will continue normal operation.
However, if the Receive DS3 Framer block receives a
DS3 frame with the FEBE bits set to a value other
than [1, 1, 1]; then it will increment the “PMON FEBE
Event Count Registers” (which are located at address
locations 0x58 and 0x59 within the Framer Address
space).
4.3.2.5.6 Detection of Change in the AIC State
Section 3.1 indicates that the “AIC” (Application Iden-
tification Channel) bit-field is the third overhead bit,
within F-Frame # 1. This particular bit-field is set to
“1” for the “C-Bit Parity” Framing Format, and is set to
“0” for the M13 Framing Format.
Hence, a given Terminal Equipment receiving a DS3
data stream can identify the framing format of this
DS3 data stream, by reading the value fo the “AIC”
bit-field. The “Receive DS3 Framer” block permits the
user’s Microcontroller/MIcroprocessor” to determine
the state of the “AIC” bit-field (within the “incoming”
DS3 data stream) by writing the value of the “AIC” bit-
field, within the most recently received DS3 frame, in-
to bit 3 (RxAIC) within the “Rx DS3 Status Register
(Address = 0x11); as illustrated below.
RXDS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
RxFERF
RxAIC
RxFEBE[2:0]
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
The Receive DS3 Framer block will also generate an field (within the incoming DS3 data stream). If this
interrupt if it detects a change of state in the AIC bit- occurs, then the Receive DS3 Framer block will set
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