XRT72L13 Datasheet, PDF (13/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

áç
PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
TABLE 36: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN RXOHCLK, (SINCE "RXO-
HFRAME" WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE
“RXOH” OUTPUT PIN ............................................................................................................... 314
Figure 108. Illustration of the signals that are output via the “Receive Overhead Output Interface (for
Method 1). ............................................................................................................................ 316
TABLE 37: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT
INTERFACE" BLOCK (METHOD 2) .............................................................................................. 317
Figure 109. Illustration of how to interface the Terminal Equipment to the “Receive Overhead Data
Output Interface” block (for Method 2). ............................................................................ 318
TABLE 38: THE RELATIONSHIP BETWEEN THE NUMBER OF “RXOHENABLE” OUTPUT PULSES ((SINCE "RXO-
HFRAME" WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING OUTPUT VIA THE
“RXOH” OUTPUT PIN ............................................................................................................... 319
Figure 110. Illustration of the signals that are output via the “Receive Overhead Data Output Inter-
face” block (for Method 2). ................................................................................................. 321
4.3.5 The Receive Payload Data Output Interface ..................................................................................... 321
Figure 111. A Simple illustration of the "Receive Payload Data Output Interface" block ............ 322
TABLE 39: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT IN-
TERFACE BLOCK ....................................................................................................................... 323
Figure 112. Illustration of the XRT72L13 DS3/E3 Framer IC being interfaced to the "Receive" Termi-
nal Equipment (Serial Mode Operation) ............................................................................ 324
Figure 113. An Illustration of the behavior of the signals between the "Receive Payload Data Output
Interface" block (of the XRT72L13) and the Terminal Equipment (Serial Mode Operation)
325
Figure 114. Illustration of the XRT72L13 DS3/E3 Framer IC being interfaced to the Receive Section
of the Terminal Equipment (Nibble-Mode Operation) ...................................................... 326
Figure 115. An Illustration of the Behavior of the signals between the “Receive Payload Data Output
Interface” Block (of the XRT72L13) and the Terminal Equipment (Nibble-Mode Operation).
327
4.3.6 Receive Section Interrupt Processing ................................................................................................ 327
BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04) ........................................................................ 328
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 328
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 329
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................ 329
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 330
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 330
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................ 330
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 331
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 331
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................ 332
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 332
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 333
RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10) ............................................................ 333
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 334
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 334
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ......................................................................................... 334
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 335
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 335
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 336
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 336
RXDS3 INTERRUPT ENABLE REGISTER (ADDRESS = 0X12) ....................................................................... 336
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 337
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................ 337
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................ 338
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................ 338
RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ................................................ 339
XI