XRT72L13 Datasheet, PDF (190/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
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PRELIMINARY
the µC/µP should toggle the WR_RW (Write
Strobe) input pin "high". This action accom-
plishes two things:
a. It latches the contents of the bi-directional data
bus into the XRT72L13 DS3 Framer Microproces-
sor Interface block.
b. It terminates the write cycle.
Figure 48 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals,
during an "Intel-type" Programmed I/O Write Opera-
tion.
FIGURE 48. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING AN "INTEL-TYPE" PROGRAMMED I/
O WRITE OPERATION
ALE_AS
A[8:0]
CS*
D[15:0]
RdB_DS
WRB_RW
Address of Target Register
Data to be Written
3.2.2.1.2 Programmed I/O Access in the Motor-
ola Mode
If the XRT72L13 DS3 Framer is interfaced to a "Mo-
torola-type" µC/µP (e.g., the MC680X0 family, etc.); it
should be configured to operate in the "Motorola"
mode (by tying the "MOTO" pin to Vcc). Motorola-
type Programmed I/O "Read" and "Write" operations
are described below.
3.2.2.1.2.1 The Motorola Mode Read Cycle
Whenever a "Motorola-type" µC/µP wishes to read
the contents of a register or some location within the
Receive LAPD Message or Receive OAM Cell Buffer,
(within the Framer device) it should do the following.
1. Assert the ALE_AS (Address-Strobe) input pin by
toggling it low. This step enables the Address
Bus input drivers, within the Microprocessor Inter-
face Block of the Framer IC.
2. Place the address of the "target" register (or
buffer location) within the Framer, on the Address
Bus input pins, A[8:0].
3. At the same time, the Address Decoding circuitry
(within the user's system) should assert the CS*
(Chip Select) input pin of the Framer device, by
toggling it "low". This action enables further com-
munication between the µC/µP and the Framer
Microprocessor Interface block.
4. After allowing the data on the Address Bus pins
to settle (by waiting the appropriate "Address
Setup" time), the µC/µP should toggle the
ALE_AS input pin "high". This step causes the
Framer device to latch the contents of the
"Address Bus" into its internal circuitry. At this
point, the address of the register or buffer loca-
tion (within the Framer) has now been selected.
5. Further, the µC/µP should indicate that this cycle
is a "Read" cycle by setting the WR_RW (R/W*)
input pin "high".
6. Next the µC/µP should initiate the current bus
cycle by toggling the Rd_DS (Data Strobe) input
pin "low". This step enables the bi-directional
data bus output drivers, within the XRT72L13
DS3 Framer device. At this point, the bi-direc-
tional data bus output drivers will proceed to
driver the contents of the "Address" register onto
the bi-directional data bus, D[7:0].
7. After some settling time, the data on the "bi-direc-
tional" data bus will stabilize and can be read by
the µC/µP. The XRT72L13 DS3 Framer will indi-
cate that this data can be read by asserting the
Rdy_Dtck (DTACK) signal.
8. After the µC/µP detects the Rdy_Dtck signal
(from the XRT72L13 DS3 Framer) it will terminate
the Read Cycle by toggling the "Rd_DS" (Data
Strobe) input pin "high".
Figure 49 presents a timing diagram which illustrates
the behavior of the Microprocessor Interface signals
during a "Motorola-type" Programmed I/O Read Op-
eration.
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