XRT72L13 Datasheet, PDF (88/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13 MULTIPLEXER/FRAMER IC
REV. 1.0.6
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PRELIMINARY
by toggling it "low". This action enables further
communication between the µC/µP and the
Framer Microprocessor Interface block.
A.4 After allowing the data on the Address Bus pins
to settle (by waiting the appropriate "Address
Setup" time), the µC/µP should toggle the
ALE_AS input pin "high". This step causes the
Framer device to latch the contents of the
Address Bus into its internal circuitry. At this
point, the "initial" address of the burst access
has now been selected.
A.5 Further, the µC/µP should indicate that this
cycle is a "Read" cycle by setting the WRB_RW
(R/W*) input pin "high".
A.6 Next the µC/µP should initiate the current bus
cycle by toggling the RdB_DS (Data Strobe)
input pin "low". This step will enable the bi-
directional data bus output drivers, within the
XRT 72L13 DS3 Framer. At this point, the bi-
directional data bus output drivers will proceed
to driver the contents of the "Address" register
onto the bi-directional data bus.
A.7 After some settling time, the data on the bi-
directional data bus will stabilize and can be
read by the µC/µP. The XRT 72L13 DS3
Framer will indicate that this data can be read
by asserting the Rdy_Dtck (DTACK) signal.
A.8 After the µC/µP detects the Rdy_Dtck signal
(from the XRT 72L13 DS3 Framer) it will termi-
nate the Read Cycle by toggling the "RdB_DS"
(Data Strobe) input pin "high".
Figure 42 presents an illustration of the behavior of
the Microprocessor Interface Signals during the "ini-
tial" Read Operation, within a Burst I/O Cycle; for a
Motorola-type µC/µP.
FIGURE 42. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE "INITIAL" READ OPERATION
OF A BURST CYCLE (MOTOROLA TYPE PROCESSOR)
ALE_AS
A[8:0]
CS*
D[15:0]
RDB_DS
WRB_RW
Rdy_Dtck
Address of “Initial” Target Register (Offset = 0x00)
Not Valid
Valid Data at Offset = 0x00
At the completion of this initial read cycle, the µC/µP
has read in the contents of the first register or buffer
location (within the XRT 72L13 DS3 Framer) for this
particular burst access operation. In order to illus-
trate how this "burst I/O cycle" works, the byte (or
word) of data, that is being read in Figure 42 has
been labeled "Valid Data at Offset = 0x00". This indi-
cates that the µC/µP is reading the very first register
(or buffer location) in this burst access.
2.2.2.2.2.1.2 The Subsequent Read Operations
The procedure that the µC/µP must use to perform
the remaining read cycles, within this Burst Access
operation, is presented below.
B.0 Execute each subsequent Read Cycle, as
described in steps B.1 through B.3, below.
B.1 Without toggling the ALE_AS input pin (e.g.,
keeping it "high"); toggle the RdB_DS (Data
Strobe) input pin "low". This step accomplishes
the following.
a. The Framer internally increments the "latched
address" value (within the Microprocessor Inter-
face circuitry).
b. The output drivers of the "bi-directional" data bus
(D[7:0]) are enabled. At some time later, the reg-
ister or buffer location corresponding to the
"incremented" latched address value will be
driven onto the bi-directional data bus.
NOTE: In order to insure that the XRT 72L13 DS3 Framer
will interpret this signal as being a "Read" signal, the µC/
µP should keep the WRB_RW input pin "High".
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