XRT72L13 Datasheet, PDF (188/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
and the other register is labeled "LSB" (or Least Sig-
nificant Byte). When an "8-bit" PMON Register is
concatenated with its "companion 8-bit" PMON Reg-
ister, one obtains the "full 16-bit expression" within
that PMON Register.
The consequence of having these 16-bit registers is
that an "8-bit" µC/µP will have to perform two consec-
utive read operations in order to read in the full 16-bit
expression contained within a given PMON register.
To complicate matters, these PMON Registers are
"Reset-Upon-Read" registers. More specifically,
these PMON Register are "Reset-Upon-Read" in the
sense that, the entire "16-bit" contents, within a given
PMON Register is reset, as soon as an "8-bit" µC/µP
reads in either "byte" of this "two-byte" (e.g., 16 bit)
expression.
For example;
Consider that an "8-bit" µC/µP needs to read in the
"PMON LCV Event Count" Register. In order to ac-
complish this task, the 8-bit µC/µP is going to have to
read in the contents of "PMON LCV Event Count
Register - MSB" (located at Address = 0x40) and the
contents of the "PMON LCV Event Count Register -
LSB (located at Address = 0x41). These two "eight-
bit" registers, when concatenated together, make up
the "PMON LCV Event Count" Register.
If the 8-bit µC/µP reads in the "PMON LCV Event
Count-LSB" register first; then the entire "PMON LCV
Event Count" register will be reset to 0x0000. As a
consequence, if the 8-bit µC/µP attempts to read in
the "PMON LCV Event Count-MSB" register in the
very next read cycle, it will read in the value 0x00.
The PMON Holding Register
In order to "get-around" this "Reset-Upon-Read"
problem, the XRT72L13 DS3 Framer includes a spe-
cial register, which permits "8-bit" µC/µP to read in
the full 16-bit contents of these PMON registers. This
special register is called the "PMON Holding" Regis-
ter; and is located at 0x56 within the Framer Address
space.
The way the PMON Holding register works is as fol-
lows. Whenever an "8-bit" µC/µP reads in one of the
bytes (of the "2-byte" PMON register); the contents of
the "unread" (e.g., other) byte will be stored in the
PMON Holding Register. Therefore, the "8-bit" µC/µP
must then read in the contents of the PMON Holding
Register in the very next read operation.
In Summary: Whenever an "8-bit" µC/µP needs to
read a PMON Register, it must execute the follow-
ing steps.
Step 1: Read in the contents of a given "8-bit" PMON
Register (it does not matter whether the µC/µP reads
in the "-MSB" or the "-LSB" register).
Step 2: Read in the contents of the "PMON Holding"
Register (located at Address = 0x56). This register
will contain the contents of the "other" byte.
3.2.2 Data Access Modes
As mentioned earlier, the Microprocessor Interface
block supports data transfer between the Framer and
the µC/µP (e.g., "Read" and "Write" operations) via
two modes: the "Programmed I/O" and the "Burst"
Modes. Each of these "Data Access" Modes are dis-
cussed in detail below.
3.2.2.1 Data Access using Programmed I/O
"Programmed I/O" is the conventional manner in
which a microprocessor exchanges data with a pe-
ripheral device. However, it is also the slowest meth-
od of data exchange between the Framer and the µC/
µP; as will be described in this text.
The next two sections present detailed information on
Programmed I/O Access, when the XRT72L13 DS3
Framer is operating in the "Intel Mode" and in the
"Motorola Mode".
3.2.2.1.1 Programmed I/O Access in the "Intel"
Mode
If the XRT72L13 DS3 Framer is interfaced to an "In-
tel-type" µC/µP (e.g., the 80x86 family, etc.), then it
should be configured to operate in the "Intel" mode
(by tying the "MOTO" pin to ground). Intel-type
"Read" and "Write" operations are described below.
3.2.2.1.1.1 The Intel Mode Read Cycle
Whenever an Intel-type µC/µP wishes to read the
contents of a register or some location within the Re-
ceive LAPD Message buffer or the Receive OAM Cell
Buffer, (within the Framer device), it should do the fol-
lowing.
1. Place the address of the "target" register or buffer
location (within the Framer) on the Address Bus
input pins A[8:0].
2. While the µC/µP is placing this address value on
the Address Bus, the Address Decoding circuitry
(within the user's system) should assert the CS*
(Chip Select) pin of the Framer, by toggling it
"low". This action enables further communication
between the µC/µP and the Framer Microproces-
sor Interface block.
3. Toggle the ALE_AS (Address Latch Enable) input
pin "high". This step enables the "Address Bus"
input drivers, within the Microprocessor Interface
block of the Framer.
4. After allowing the data on the Address Bus pins
to settle (by waiting the appropriate "Address"
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