XRT72L13 Datasheet, PDF (220/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
áç
PRELIMINARY
Setting this bit-field to “1” configures M12 # 2 to
support ITU-T G.747. In this mode, the M12 MUX will
accept 3 E1 signals (via TxDS1Data4 thru
TxDS1Data6) and will multiplex these signals into an
ITU-T G.747 signal. Likewise, the M12 DEMUX will
accept an incoming ITU-T G.747 signal (from the
M23 DEMUX) and will de-multiplexe this signal into 3
E1 signals. These three E1 signals will output via the
“RxDS1Data4” thru “RxDS1Data6” output pins.
Bit 3 - M12G.747 Reserved
Bit 2 - M12 FERF
This “Read/Write” bit-field permits the user to force
M12 MUX # 2 to transmit a “FERF” (Far-End-Receive
Failure) indicator to the M23 MUX (and in turn to the
remote terminal equipment).
Setting this bit-field to “1” configures the M12 MUX to
set the “X-bits” (within the “outbound” DS2 data
stream) to “0”. This signaling will be interpreted (by
the remote terminal equipment) as a FERF indicator.
Settiing this bit-field to “0” configures the M12 MUX to
set the “X-bits” (within the “outbound” DS2 data
stream) to “1”. This signaling will be interpreted (by
the remote terminal equipment) as an indication of no
FERF.
Bits 1 and 0 M12 LB Code[1:0]
3.3.2.25 M12 DS2 # 3 Configuration Register
)
M12 DS2 # 3 CONFIGURATION REGISTER (ADDRESS = 0X1C)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
7
Reserved
6
M12
Bypass
M12
G.747
M12
M12 FERF
G.747 Res
M12LBCode[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1
1
1
Bit 7 - Reserved
This bit-field must be set to “0”, in order for the
XRT72L13 M13 device to function properly.
Bit 6 - Reserved
This bit-field must be set to “0” in order for the
XRT72L13 M13 device to function properly.
Bit 5 - M12 Bypass
This “Read/Write” bit field permits the user to bypass
M12 Multiplexer/De-Multiplexer # 3. By doing this the
following will happen.
In the Transmit Direction
• The XRT72L13 M13 device will accept a DS2 clock
signal (6.312MHz) via the TxDS1Clk11 input pin.
• The XRT72L13 M13 device will accept a DS2 sig-
nal via the TxDS1Data_11 input pin
In the Receive Direction
• The XRT72L13 M13 device will output a DS2 clock
signal (6.312MHz) via the RxDS1Clk11 output pin.
• XRT72L13 M13 device will output the contents of
DS2 Channel # 2 via the RxDS1Data11 output pin.
Setting this bit-field to “1” configures M12 MUX # 3
and M12 DEMUX # 3 to be bypassed.
Setting this bit-field to “0” enables M12 MUX # 3 and
M12 DEMUX # 3.
Bit 4 - M12 G.747
This “Read/Write” bit-field permits the user to config-
ure M12 MUX # 3 and DEMUX # 3 to support either a
DS2 signal or an ITU-T G.747 signal.
Setting this bit-field to “0” configures M12 # 3 to sup-
port DS2. In this mode, the M12 MUX will accept four
DS1 signals (via TxDS1Data8 thru TXDS1Data11)
and will muitiplex these signals into a DS2 signal.
Likewise, the M12 DEMUX will accept an incoming
DS2 signal (from the M23 DEMUX) and will de-multi-
plex this signal into 4 DS1 signals. These four DS1
signals will be output via the “RxDS1Data8” thru
“RxDS1Data11” output pins.
Setting this bit-field to “1” configures M12 # 3 to sup-
port ITU-T G.747. In this mode, the M12 MUX will ac-
cept 3 E1 signals (via TxDS1Data8 thru
TxDS1Data10) and will multiplex these signals into
an ITU-T G.747 signal. Likewise, the M12 DEMUX
will accept an incoming ITU-T G.747 signal (from the
M23 DEMUX) and will de-multiplexe this signal into 3
E1 signals. These three E1 signals will output via the
“RxDS1Data8” thru “RxDS1Data10” output pins.
Bit 3 - M12G.747 Reserved
Bit 2 - M12 FERF
This “Read/Write” bit-field permits the user to force
M12 MUX # 3 to transmit a “FERF” (Far-End-Receive
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