XRT72L13 Datasheet, PDF (311/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
The "Receive DS3 Framer" block circuitry includes an
"Up/Down" Counter that is used to track the number
of "M-frames" that have been identified as exhibiting
the "Idle Condition" by the "Receive DS3 Framer"
block. The contents of this counter are set to zero up-
on reset or power up. This counter is then increment-
ed whenever the "Receive DS3 Framer" block detects
an "Idle-type" M-frame. The counter is decremented,
or kept at zero if a "non-Idle" M-frame is detected. If
the "Receive DS3 Framer" block detects a sufficient
number of "Idle-type" M-frames, such that the counter
reaches the number "63", then the "Receive DS3
Framer" block will declare the "Idle Condition". Ex-
plained another way, the "Receive DS3 Framer" block
will declare an "Idle Condition" if the number of "Idle-
Pattern" M-frames is detected such that it meets the
following conditions.
NIDLE - NVALID > 63,
where:
NIDLE = the number of M-frames containing the "Idle
Pattern"
NVALID = the number of M-frames not exhibit the
"Idle Pattern"
Anytime the contents of this "Up/Down" Counter
reaches the number 63, then the "Receive DS3 Fram-
er" block will:
1. Set Bit 5 (Rx Idle) within the "Rx DS3 Configura-
tion and Status" Register, to "1" as depicted
below.
RX DS3 CONFIGURATION AND STATUS REGIS-
TER, (ADDRESS = 0X10)
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1
BIT 0
Rx AIS
Rx LOS
Rx Idle
Rx OOF
Int LOS
Disable
Framing on F-Sync Algo M-Sync Algo
Parity
R/O
R/O
R/O
R/O
R/W
R/W
R/W
R/W
X
X
1
X
X
X
X
X
2. Generate a "Change in Idle Status" Interrupt
Request to the local µP/µC.
The "Receive DS3 Framer" block will clear the "Idle
Condition" if it has detected a sufficient number of
"Non-Idle" M-frames, such that this "Up/Down"
Counter reaches the value "0".
4.3.2.5.4 The Detection of (FERF) or "Yellow
Alarm" Condition
The "Receive DS3 Framer" block will identify and de-
clare a "Yellow Alarm" condition or a "Far-End Re-
ceive Failure" (FERF) condition, if it starts to receive
DS3 frames with both of its X-bits set to "0".
When the "Receive DS3 Framer" block detects a
"FERF" condition in the incoming DS3 frames, then it
will then do the following.
1. It will assert the "RxFERF" (bit-field 4) within the
Rx DS3 Status Register, as depicted below.
RX DS3 STATUS REGISTER (ADDRESS = 0X11)
BIT 7
BIT 6
BIT 5
BIT 4
Not Used
Rx FERF
RO
RO
RO
RO
0
0
0
1
This bit-field will remain asserted for the duration that
the "Yellow Alarm" condition exists.
2. The "Receive DS3 Framer" block will also gener-
ate a "Change in FERF Status" interrupt to the
BIT 3
BIT2
BIT 1
BIT 0
RxAIC
RxFEBE [2] RxFEBE [1] RxFEBE [0]
RO
RO
RO
RO
X
X
X
X
µP/µC. Consequently, the "Receive DS3 Framer"
block will also assert the "FERF Interrupt Status"
bit, within the Rx DS3 Interrupt Status Register,
as depicted below.
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