XRT72L13 Datasheet, PDF (108/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13 MULTIPLEXER/FRAMER IC
REV. 1.0.6
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PRELIMINARY
This bit-field will be asserted under either of the fol-
lowing conditions.
a. When the Receive DS3 Framer block first
detects the occurrence of a “FERF” condition in the
“inbound” DS3 data stream (e.g., all X-bits are set
to “0”).
b. When the Receive DS3 Framer block no longer
detects the “FERF” condition in the “inbound” DS3
data stream (e.g., all X-bits are set to “1”).
The Microprocessor/Microcontroller can determine
the state of the of the “FERF” condition by reading bit
4 within the “Rx DS3 Status” register (Address loca-
tion = 0x11).
NOTE: For more information about the “FERF” condition,
please see Section _.
Bit 2 - Change in AIC State Interrupt Status
This “Reset-upon-Read” bit-field is set to “1” if the AIC
bit-field, within the incoming DS3 data stream, has
changed state since the last read of this register.
The Microprocessor/Microcontroller can determine
the state of the “AIC” bit-field by reading bit 3, within
the “Rx DS3 Status” Register (Address location =
0x11).
NOTE: For more information on this interrupt condition,
please see Section _.
Bit 1 - Change in OOF Condition Interrupt Status
The “Reset-upon-Read” bit-field is set to “1” if the
“Receive DS3 Framer” block (within the XRT72L13)
has detected a “Change in the Out-of-Frame” (OOF)
condition, since the last time this register was read.
This bit-field will be asserted under either of the fol-
lowing conditions.
a. When the “Receive DS3 Framer” block has
detected the appropriate condition to declare an
“OOF” condition.
b. When the “Receive DS3 Framer” block has tran-
sitioned from the “OOF” condition (Frame Acquisi-
tion Mode).
The Microprocessor/Microcontroller can detemine the
state of the “OOF” condition by reading bit 4 within
the “Rx DS3 Configuration and Status” Register (Ad-
dress location = 0x10).
NOTE: For more information about the “OOF” condition,
please see Section _.
Bit 0 - Detection of P-Bit Error Interrupt Status
This “Reset-upon-Read” bit-field indicates whether or
not the “Detection of P-Bit Error” interrupt has oc-
curred since the last read of this register.
This bit-field will be “0” if the “Receive DS3 Framer”
block (within the XRT72L13 M13 device) has not de-
tected a P-bit error since the last read of this register.
Conversely, this bit-field will be “1” if the “Receive
DS3 Framer” block (within the XRT72L13 M13 de-
vice) has detected a P-Bit error since the last read of
this register.
2.3.2.19 RxDS3 Sync Detect Register
RX DS3 SYNC DETECT REGISTER (ADDRESS = 0X14)
BIT 7
Not Used
R/O
0
BIT 6
Not Used
R/O
0
BIT 5
Not Used
R/O
0
BIT 4
Reserved
R/O
0
BIT 3
Reserved
R/O
0
BIT 2
Reserved
R/O
0
BIT 1
F
Algorithm
R/W
0
BIT 0
One and
Only One
R/W
0
Bit 1 - F Algorithm
To be provided in the next revision.
Bit 0 - One and Only One
RXDS3 FEAC REGISTER (ADDRESS = 0X16)
To be provided in the next revision.
2.3.2.20 RxDS3 FEAC Register
BIT 7
Not Used
R/O
0
BIT 6
R/O
1
BIT 5
R/O
1
BIT 4
BIT 3
RxFEAC[5:0]
R/O
R/O
1
1
BIT 2
R/O
1
BIT 1
R/O
1
BIT 0
Not Used
R/O
0
This "Read/Write" register contains the latest 6-bit
FEAC code that has been "validated" by the Receive
FEAC Processor. The contents of this register will be
cleared if the previously "validated" code has been
"removed" by the FEAC Processor.
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