XRT72L13 Datasheet, PDF (365/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
Once the user implements this configuration setting
then M12 DEMUX # 1 will be configured to operate in
the DS1” Mode. When M12 DEMUX # 1 is operating
in the “DS1” Mode, then it will then be configured to
accept a DS2 signal, and de-multiplex this signal into
4 DS1 signals. M12 DEMUX # 1 will then output this
signal (via the “RxDS1Data_0” through
“RxDS1Data_3” output pins). M12 DEMUX # 1 will
output this demultiplexed data upon the rising edges
of “RxDS1Clk_0” through “RxDS1Clk_3”.
Configuring the remaining M12 DEMUX Blocks
The remaining M12 DEMUX blocks (e.g., M12 DE-
MUX Block numbers 2 thorugh 7) can also be config-
ured to operate in the “DS1” Mode, by setting Bits 4
(M12 G.747) and Bit 5 (M12 Bypass) to “0”, within
each of their corresponding “M12 DS2 Configuration”
Registers (Address Locations: 0x1B through 0x20).
5.3.1.2.1.2 Additional Roles of the M12 DEMUX
Blocks - DS1 Mode
As the M12 DEMUX block accepts the DS2 data
stream and de-multiplexes it into 4 DS1 signals, the
M12 DEMUX block will also do the following.
• It will acquire and maintain DS2 synchronization
(via the “F” and “M” bits). If the M12 DEMUX were
to fail to maintain DS2 frame synchronization, then
it will declare a “DS2 OOF” condition.
• It will also detect and declare a “DS2 AIS” and “DS2
FERF” condition.
• It will detect and flag the occurrences of “F” and “M”
bit errors.
5.3.1.2.1.2.1 Declaring and Clearing the DS2
OOF Condition
It a given M12 DEMUX declares a “DS2 OOF” condi-
tion, then it will do so by setting Bit 4 (DS2 OOF Sta-
tus), within the corresponding “DS2 Framer Status”
Register to “1”. An illustration of Bit 4 being set to “1”,
within the “DS2 # 1 Framer Status” Register, is pre-
sented below.
DS2 # 1 FRAMER STATUS REGISTER (ADDRESS = 0XA3)
BIT 7
BIT 6
Unused
R/O
R/O
0
0
BIT 5
DS2 COFA
Status
R/W
0
BIT 4
DS2 OOF
Status
R/W
1
BIT 3
DS2 FERF
Status
R/W
0
BIT 2
DS2 RED
Alarm
Status
R/W
0
BIT 1
DS2 AIS
Status
R/W
0
BIT 0
DS2
RESV
Status
R/W
0
NOTE: The M12 DEMUX will also generate a “Change in
DS2 OOF Condition” Interrupt, if it detects or clears the
“DS2 OOF” condition.
When the M12 DEMUX ceases to declares the “DS2
OOF” condition, then it will set this bit-field back to
“0”, in order to reflect “normal” operation.
NOTE: The locations of the remaining “DS2 Framer Status”
register (for the remaining M12 DEMUX blocks) are at
Address locations 0xA4 through 0xA9.
5.3.1.2.1.2.2 Declaring and Clearing the DS2
AIS Condition
It a given M12 DEMUX declares a “DS2 AIS” condi-
tion, then it will do so by setting Bit 2 (DS2 AIS Sta-
tus), within the corresponding “DS2 Framer Status”
Register to “1”. An illustration of Bit 4 being set to “1”,
within the “DS2 # 1 Framer Status” Register, is pre-
sented below.
DS2 # 1 FRAMER STATUS REGISTER (ADDRESS = 0XA3)
BIT 7
BIT 6
Unused
R/O
R/O
0
0
BIT 5
DS2 COFA
Status
R/W
0
BIT 4
DS2 OOF
Status
R/W
0
BIT 3
DS2 FERF
Status
R/W
0
BIT 2
DS2 RED
Alarm
Status
R/W
0
BIT 1
DS2 AIS
Status
R/W
1
BIT 0
DS2
RESV
Status
R/W
0
NOTE: The M12 DEMUX will also generate a “Change in
DS2 AIS Condition” Interrupt, if it detects or clears the “DS2
AIS” condition.
When the M12 DEMUX ceases to declares the “DS2
AIS” condition, then it will set this bit-field back to “0”,
in order to reflect “normal” operation.
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