XRT72L13 Datasheet, PDF (3/370 Pages) Exar Corporation – M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

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PRELIMINARY
XRT72L13
M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC
REV. P1.0.6
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................. 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1. Block Diagram of the XRT72L13 Multiplexer/Framer ........................................................... 1
PIN OUT OF THE 72L13 FRAMER IC ............................................................................................................... 2
ORDERING INFORMATION ...................................................................................................................... 2
ELECTRICAL CHARACTERISTICS ................................................................................. 39
ABSOLUTE MAXIMUMS ................................................................................................................................ 39
DC ELECTRICAL CHARACTERISTICS ............................................................................................................ 39
AC ELECTRICAL CHARACTERISTICS ............................................................................................................ 39
AC ELECTRICAL CHARACTERISTICS (CONT.) ............................................................................................... 40
Figure 2. Timing Diagram for Transmit Payload Input Interface, when the XRT72L13 is operating in
both the DS3 and Loop-Timing Modes ................................................................................ 43
Figure 3. Timing Diagram for the Transmit Payload Input Interface, when the XRT72L13 is operating
in both the DS3/Serial and Local-Timing Modes ................................................................ 44
Figure 4. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L13 is op-
erating in both the DS3/Nibble and Looped-Timing Modes .............................................. 44
Figure 5. Timing Diagram for the Transmit Payload Data Input Interface, when the XRT72L13 is op-
erating in the DS3/Nibble and Local-Timing Modes ........................................................... 45
Figure 6. Timing Diagram for the Transmit Overhead Data Input Interface (Method 1 Access) .... 45
Figure 7. Timing Diagram for the Transmit Overhead Data Input Interface (Method 2 Access) .... 46
Figure 8. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on
the rising edge of "TxLineClk" ............................................................................................. 46
Figure 9. Transmit LIU Interface Timing - Framer is configured to update "TxPOS" and "TxNEG" on
the falling edge of "TxLineClk" ............................................................................................ 47
Figure 10. Receive LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG"
on the rising edge of "RxLineClk" ....................................................................................... 47
Figure 11. Receiver LIU Interface Timing - Framer is configured to sample "RxPOS" and "RxNEG"
on the falling edge of "RxLineClk" ...................................................................................... 48
Figure 12. Receive Payload Data Output Interface Timing (Serial Mode Operation) ...................... 48
Figure 13. Receive Payload Data Output Interface Timing (Nibble Mode Operation) ..................... 49
Figure 14. Receive Overhead Data Output Interface Timing (Method 1 - Using RxOHClk) ............ 49
Figure 15. Receive Overhead Data Output Interface Timing (Method 2 - Using RxOHEnable) ..... 50
Figure 16. Microprocessor Interface Timing - Intel Type Programmed I/O Read Operations ........ 50
Figure 17. Microprocessor Interface Timing - Intel Type Programmed I/O Write Operations ....... 51
Figure 18. Microprocessor Interface Timing - Intel Type Read Burst Access Operation ............... 51
Figure 19. Microprocessor Interface Timing - Intel Type Write Burst Access Operation .............. 52
Figure 20. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation .. 52
Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation .. 53
Figure 22. Microprocessor Interface Timing - Motorola Type Read Burst Access Operation ....... 53
Figure 23. Microprocessor Interface Timing - Motorola Type Write Burst Access Operation ....... 53
Figure 24. Microprocessor Interface Timing - ResetB* Pulse Width ................................................ 53
1.0 SYSTEM DESCRIPTION ................................................................................................................... 54
Figure 25. Block Diagram of the XRT72L13 M13 Multiplexer/Framer IC .......................................... 54
1.1 XRT72L13 OPERATION WHILE IN THE MULTIPLEXER/DE-MULTIPLEXER MODE ................................. 54
Figure 26. Functional Block Diagram of the XRT72L13 M13 Multiplexer/Framer IC, while operating
in the "Multiplexer/De-Multiplexer Mode ............................................................................. 55
1.1.1 In the Transmit Direction ...................................................................................................................... 55
1.1.2 In the Receive Direction ....................................................................................................................... 56
1.1.3 Diagnostic Resources available for MUX/DEMUX Mode ..................................................................... 56
Figure 27. Illustration of the XRT72L13 Operating in the "DS1/E1 Tributary Loop-back Mode ..... 57
Figure 28. Illustration of the XRT72L13 Operating in the "DS2/ITU-T G.747 Tributary Loop-Back
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